A Distributed Canny Edge Detector: Algorithm and FPGA Implementation

2014 ◽  
Vol 23 (7) ◽  
pp. 2944-2960 ◽  
Author(s):  
Qian Xu ◽  
Srenivas Varadarajan ◽  
Chaitali Chakrabarti ◽  
Lina J. Karam
Keyword(s):  
Fpga Implementation ◽  
Edge Detector ◽  
Canny Edge Detector ◽  
Canny Edge

Short Hand Recognition using Canny Edge Detector

2017 ◽  
Vol 7 (5) ◽  
pp. 902-907
Author(s):  
Pramod Kumar S ◽  
◽  
Narendra T.V ◽  
Vinay N.A ◽  
◽  
...  
Keyword(s):  
Edge Detector ◽  
Canny Edge Detector ◽  
Canny Edge ◽  
Short Hand ◽  
Hand Recognition

Fine structure measurement in the SEM cross section of LSI using the Canny edge detector

2003 ◽  
Author(s):  
Yoshihiro Midoh ◽  
Katsuyoshi Miura ◽  
Koji Nakamae ◽  
Hiromu Fujioka
Keyword(s):  
Fine Structure ◽  
Cross Section ◽  
Edge Detector ◽  
Canny Edge Detector ◽  
Canny Edge ◽  
Structure Measurement

scholarly journals SURVEY ON DISTRIBUTED CANNY EDGE DETECTOR WITH FPGA

2015 ◽  
Vol 3 (3) ◽  
pp. 51-61
Author(s):  
Poonam S. Deokar ◽  
Anagha P. Khedkar
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Large Scale ◽  
Attractive Alternative ◽  
Edge Detector ◽  
Canny Edge Detection ◽  
Canny Edge Detector ◽  
Canny Edge ◽  
Canny Algorithm ◽  
Real Time Applications

The Edge can be defined as discontinuities in image intensity from one pixel to another. Modem image processing applications demonstrate an increasing demand for computational power and memories space. Typically, edge detection algorithms are implemented using software. With advances in Very Large Scale Integration (VLSI) technology, their hardware implementation has become an attractive alternative, especially for real-time applications. The Canny algorithm computes the higher and lower thresholds for edge detection based on the entire image statistics, which prevents the processing of blocks independent of each other. Direct implementation of the canny algorithm has high latency and cannot be employed in real-time applications. To overcome these, an adaptive threshold selection algorithm may be used, which computes the high and low threshold for each block based on the type of block and the local distribution of pixel gradients in the block. Distributed Canny Edge Detection using FPGA reduces the latency significantly; also this allows the canny edge detector to be pipelined very easily. The canny edge detection technique is discussed in this paper.

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