A Reply to Comments on “New Algorithm for Measuring 50/60 Hz AC Values Based on the Usage of Slow A/D Converters” and “Measuring of Slowly Changing AC Signals Without Sample-and-Hold Circuit”

2006 ◽  
Vol 55 (5) ◽  
pp. 1859-1862 ◽  
Author(s):  
P. Petrovic ◽  
M. Stevanovic
Keyword(s):  
Sample And Hold

Optically strobed sample-and-hold circuit

1987 ◽  
Vol 23 (5) ◽  
pp. 234-235
Author(s):  
C. McConaghy
Keyword(s):  
Sample And Hold

scholarly journals An 8-Channel Sample-and-Hold with Multiplexed Analog Output

1973 ◽  
Vol 20 (1) ◽  
pp. 216-220 ◽  
Author(s):  
A. K. Chang ◽  
R. S. Larsen
Keyword(s):  
Sample And Hold ◽  
Analog Output

Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine

2016 ◽  
Vol 63 (4) ◽  
pp. 366-370 ◽  
Author(s):  
Dariusz Koscielnik ◽  
Dominik Rzepka ◽  
Jakub Szyduczynski
Keyword(s):  
Sigma Delta ◽  
Sample And Hold ◽  
Time Encoding

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

2013 ◽  
Vol 473 ◽  
pp. 50-53
Author(s):  
Jie Lin ◽  
Fei Yan Mu
Keyword(s):  
Dynamic Range ◽  
Harmonic Distortion ◽  
High Accuracy ◽  
Pipeline Adc ◽  
Nonlinearity Error ◽  
Front End ◽  
Sample And Hold ◽  
Spurious Free Dynamic Range ◽  
Bicmos Process ◽  
Free Dynamic

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

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