Signature Analyzer Design for Yield Learning Support

Abstract Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

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Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

10.31399/asm.cp.istfa2018p0300 ◽

2018 ◽

Author(s):

Seng Nguon Ting ◽

Hsien-Ching Lo ◽

Donald Nedeau ◽

Aaron Sinnott ◽

Felix Beaudoin

Keyword(s):

Failure Analysis ◽

High Performance ◽

Yield Loss ◽

Technology Development ◽

High Density ◽

High K ◽

Yield Learning ◽

Oxide Deposition ◽

Edge Profile ◽

High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2005p0501 ◽

2005 ◽

Author(s):

Chris Eddleman ◽

Nagesh Tamarapalli ◽

Wu-Tung Cheng

Keyword(s):

Failure Analysis ◽

Fault Location ◽

Effective Means ◽

Fault Isolation ◽

Yield Enhancement ◽

Yield Analysis ◽

Isolation Techniques ◽

Yield Learning ◽

Time Required ◽

Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

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