Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard

<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

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High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v6i1.8388 ◽

2016 ◽

Vol 6 (1) ◽

pp. 298 ◽

Cited By ~ 1

Author(s):

Soufiane Oukili ◽

Seddik Bri

Keyword(s):

High Throughput ◽

Data Encryption ◽

Fpga Implementation ◽

Time Variable ◽

Digital Data ◽

Data Encryption Standard ◽

Gate Arrays ◽

Hardware Implementations ◽

Symmetric Key ◽

Legacy Applications

<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

Download Full-text