B-algorithm: a behavioral test generation algorithm

2002 ◽  
Author(s):  
Chang Hyun Cho ◽  
J.R. Armstrong
Keyword(s):  
Test Generation ◽  
Behavioral Test ◽  
Generation Algorithm

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli
Keyword(s):  
Temporal Logic ◽  
Test Generation ◽  
Digital Circuits ◽  
Difficult Problem ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Temporal Behavior ◽  
Generation Algorithm

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

Behavioral test generation/fault simulation

2003 ◽  
Vol 22 (1) ◽  
pp. 27-32 ◽  
Author(s):  
Chien-In Henry Chen
Keyword(s):  
Test Generation ◽  
Fault Simulation ◽  
Behavioral Test

scholarly journals Test Generation Algorithm for Fault Detection of Analog Circuits Based on Extreme Learning Machine

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Jingyu Zhou ◽  
Shulin Tian ◽  
Chenglin Yang ◽  
Xuelong Ren
Keyword(s):  
Extreme Learning Machine ◽  
Analog Circuits ◽  
Test Generation ◽  
Cost Effective ◽  
Fault Classification ◽  
The Novel ◽  
Analog Device ◽  
Generation Algorithm ◽  
New Process ◽  
Learning Machine

This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments.

How an "evolving" fault model improves the behavioral test generation

2002 ◽  
Author(s):  
G. Buonanno ◽  
F. Ferrandi ◽  
L. Ferrandi ◽  
F. Fummi ◽  
D. Sciuto
Keyword(s):  
Test Generation ◽  
Fault Model ◽  
Behavioral Test
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