QML (qualified manufacturing line): a method of providing high quality integrated circuits

2002 ◽  
Author(s):  
N.E. Donlin
Keyword(s):  
Integrated Circuits ◽  
High Quality ◽  
Manufacturing Line

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

scholarly journals Table of contents and Foreword

2007 ◽  
Vol 2 (1) ◽  
pp. 1-6
Author(s):  
João Antonio Martino ◽  
Luigi Carro
Keyword(s):  
Integrated Circuits ◽  
Systems Design ◽  
Technical Committee ◽  
High Quality

This issue of Journal of Integrated Circuits and Systems (JICS) includes 6 papers on design, test and CAD. These papers have been selected from the presentations given at SBCCI2006 (Symposium on Integrated Circuits and Systems Design), which was organized in Ouro Preto, Brazil in 2006. Among the contributions presented at SBCCI2006 conference, only a few were selected by the Technical Committee for this issue. These papers have been submitted to usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection which guarantees the scientic level of this issue.We sincerely hope that JICS readers will enjoy these contributions, as we have enjoyed listening to them at the SBCCI2006 conference.  The Editors.

scholarly journals Table of Contents and Foreword

2009 ◽  
Vol 4 (2) ◽  
pp. 46-50
Author(s):  
João Antonio Martino ◽  
Marcelo Lubaszewski
Keyword(s):  
Integrated Circuits ◽  
Extended Version ◽  
High Quality ◽  
Scientific Level ◽  
Microelectronics Technology ◽  
Soi Technology

This issue of Journal of Integrated Circuits and Systems (JICS) includes papers on process, materials, devices, and modeling. These papers have been selected from the presentations given at SBMicro2008 (23rd Symposium on Microelectronics Technology and Devices), which has been held in Gramado, Brazil in 2008. Among the contributions presented at SBMicro2008 conference, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to usual reviewing process with the help of external experts. An invited paper from Dr. Carlos Mazure on SOI technology and its applications is included in this issue and also spontaneous submissions have been considered. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.João Antonio Martino - JICS Editor-in-chiefMarcelo Lubaszewski - JICS Co-Editor

scholarly journals Sample preparation for aberration-corrected microscopy of high-quality TEM specimens of advanced integrated circuits

2018 ◽  
Vol 24 (S1) ◽  
pp. 150-151
Author(s):  
C.S. Bonifacio ◽  
M. Campin ◽  
K. McIlwrath ◽  
M. Ray ◽  
P.E. Fischione
Keyword(s):  
Integrated Circuits ◽  
Sample Preparation ◽  
High Quality ◽  
Aberration Corrected

scholarly journals Photonic Crystal Cavity with a Thin Low-Index Layer for Silicon-Compatible Nanolight Source

2018 ◽  
Vol 8 (9) ◽  
pp. 1552 ◽  
Author(s):  
Youngsoo Kim ◽  
Young Lee ◽  
Seokhyeon Hong ◽  
Kihwan Moon ◽  
Soon-Hong Kwon
Keyword(s):  
Photonic Crystal ◽  
Integrated Circuits ◽  
Quality Factor ◽  
Wavelength Region ◽  
High Quality Factor ◽  
Silica Layer ◽  
High Quality ◽  
Light Emitting ◽  
Telecommunication Wavelength ◽  
Silicon Based

The development of an efficient silicon-based nanolight source is an important step for silicon-based photonic integrated circuits. We propose a high quality factor photonic crystal nanocavity consisting of silicon and silica, which can be used as a silicon-compatible nanolight source. We show that this cavity can effectively confine lights in a low-index silica layer with a high confinement factor of 0.25, in which rare-earth dopants can be embedded as gain materials. The cavity is optimized to have a high quality factor of 15,000 and a mode volume of 0.01 μm3, while the resonance has a wavelength of 1537 nm. We expect that the high confinement factor in the thin silica layer and the high quality factor of the proposed cavity enable the cavity to be a good candidate for silicon-compatible nanolight sources for use in nanolasers or light-emitting diodes in the telecommunication wavelength region.

Novel Mocvd Processes for Nanoscale Oxide Thin Films

1996 ◽  
Vol 446 ◽  
Author(s):  
Tingkai Li ◽  
Pete Zawadzkp ◽  
Richard A. Stall ◽  
Yongfei Zhu ◽  
Seshu B. Desu
Keyword(s):  
Thin Films ◽  
Surface Roughness ◽  
Integrated Circuits ◽  
Deposition Temperature ◽  
High Dielectric Constant ◽  
Ferroelectric Properties ◽  
Oxide Thin Films ◽  
High Quality ◽  
Step Process ◽  
High Dielectric

AbstractNanoscale oxide thin films such as Ba1‐xSrxTiO3 (BST), SrBi2Ta2O9 (SBT), and PbZr1‐xTixO3 (PZT) that have a high dielectric constant and excellent ferroelectric properties have been receiving greatly increased attention, especially for high density memories in next generation integrated circuits. However, with increasing deposition temperature the surface roughness of the films increases, which results in high leakage current, and when the thickness of oxide films is decreased, the apparent bulk‐like properties of thin films tend to worsen due to the increased influence of the interface. To solve these problems, novel MOCVD techniques, plasma enhanced deposition, and a two step process, were developed for high quality oxide thin films.

scholarly journals In situ growth of large-area and self-aligned graphene nanoribbon arrays on liquid metal

2020 ◽  
Author(s):  
Le Cai ◽  
Wanzhen He ◽  
Xudong Xue ◽  
Jianyao Huang ◽  
Ke Zhou ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Graphene Nanoribbons ◽  
Chemical Vapour ◽  
Copper Surface ◽  
In Situ Growth ◽  
Large Area ◽  
High Quality ◽  
Hydrogen Flow ◽  
Template Free

Abstract Intrinsic graphene features semi-metallic characteristics that limit its applications in electronic devices, whereas graphene nanoribbons (GNRs) are promising semiconductors owing to their bandgap-opening feature. However, the controllable mass-fabrication of high-quality GNR arrays remains a major challenge. In particular, the in situ growth of GNR arrays through template-free chemical vapour deposition (CVD) has not been realized. Herein, we report a template-free CVD strategy to grow large-area, high-quality, and self-aligned GNR arrays on the liquid copper surface. The width of as-grown GNR could be optimized to sub-10 nm with aspect ratio up to 387, which is higher than those of reported CVD-GNRs. The study of the growth mechanism indicates that a unique comb-like etching-regulated growth process caused by a trace hydrogen flow guides the formation of the mass-produced self-aligned GNR arrays. Our approach is operationally simple and efficient, offering an assurance for the use of GNR arrays in integrated circuits.

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