Clock signal distribution network for high speed testers

2003 ◽  
Author(s):  
C.-W. Hsue
Keyword(s):  
High Speed ◽  
Distribution Network ◽  
Clock Signal ◽  
Signal Distribution

A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP

2007 ◽  
Vol 16 (01) ◽  
pp. 51-63
Author(s):  
CHI-CHOU KAO
Keyword(s):  
High Speed ◽  
Distribution Network ◽  
Clock Signal ◽  
Clock Distribution ◽  
Single Chip ◽  
New Approach ◽  
Flexibility Design ◽  
Clock Distribution Network ◽  
On Chip ◽  
High Flexibility

The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.

Polymer waveguide-based high-speed clock signal distribution system

1997 ◽  
Author(s):  
Ting Li ◽  
Suning Tang ◽  
Randy W. Wickman ◽  
Linghui Wu ◽  
Feiming Li ◽  
...  
Keyword(s):  
Distribution System ◽  
High Speed ◽  
Clock Signal ◽  
Signal Distribution ◽  
Polymer Waveguide

SIMULATION SCHEME MODELING OF THE SUPER-SPEED TIME BUFFER

2020 ◽  
Author(s):  
А.М. САЖНЕВ ◽  
Л.Г. РОГУЛИНА
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Low Cost ◽  
Circuit Modeling ◽  
Clock Signal ◽  
Behavioral Models ◽  
Software Environment ◽  
Time Buffer ◽  
The Given ◽  
Simulation Scheme

Приводятся результаты моделирования сверхскоростного буфера тактовых сигналов, выполненного на базе арсенид-галлиевых n-канальных транзисторов в среде OrCAD и полностью отвечающего следующим требованиям: высокие технические характеристики, малые размеры, высокая частота и КПД, гибкость применения. Приведенные поведенческие модели допускают использование любой программной среды по схемотехническому моделированию. The results of simulation of an ultra-high-speed clock signal buffer based on gallium arsenide n-channel transistors in OrCAD are presented, which fully meets the following requirements: high technical characteristics, application flexibility, low cost, small size, high frequency, and high efficiency. The given behavioral models allow the use of any software environment for circuit modeling.

Design of Equivalent Sampling Based on Printed Circuit Board Suited for Power Communication System

2013 ◽  
Vol 333-335 ◽  
pp. 465-471
Author(s):  
Chuan Liu ◽  
Zhi Chao Huang ◽  
Peng Wu ◽  
Lei Chen ◽  
Wei Wang
Keyword(s):  
Time Delay ◽  
Communication System ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Transmission Time ◽  
Clock Signal ◽  
Signal Delay ◽  
Printed Circuit ◽  
Sequential Logic

Many applications in Power communication system have a demand of adjustable transmission time delay of high-speed signal. In sequential logic circuit, the control of transmission time delay of high-speed signal can effectively improve the accuracy of clock sampling, as a result, satisfy the constraints between clock signal and periodic data. A method of equivalent sampling based on printed circuit board (PCB) is provided in the article, it realizes equivalent sampling of the data by fixing a group of clock signal delay, thus, increase the accuracy of sampling.

scholarly journals Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits

2017 ◽  
Vol 2017 ◽  
pp. 1-10 ◽  
Author(s):  
Khaoula Ait Belaid ◽  
Hassan Belahrach ◽  
Hassan Ayad
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Electromagnetic Coupling ◽  
Distribution Network ◽  
Switching Noise ◽  
Power Distribution Network ◽  
Vector Fitting ◽  
Rational Function Approximation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix Y of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.

Polyimide-based guided-wave multigigabit per second optical clock signal distribution system for Cray T-90 supercomputer

1998 ◽  
Author(s):  
Hong-Fa Luan ◽  
Linghui Wu ◽  
Bipin Bihari ◽  
Jianhua Gan ◽  
Ray T. Chen ◽  
...  
Keyword(s):  
Distribution System ◽  
Guided Wave ◽  
Optical Clock ◽  
Clock Signal ◽  
Signal Distribution
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