A PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence

2006 ◽  
Author(s):  
Tomoaki Sato ◽  
Kazuhira Kikuchi ◽  
Masa-aki Fukase
Keyword(s):  
Low Power ◽  
High Speed ◽  
Random Number ◽  
Number Sequence

A Compact and Low Power Realization of a High Frequency Chaotic Oscillator

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-27
Author(s):  
R. Chase Harrison ◽  
Benjamin K. Rhea ◽  
Frank T. Werner ◽  
Robert N. Dean
Keyword(s):  
Low Power ◽  
Chaotic System ◽  
High Frequency ◽  
High Speed ◽  
Random Number ◽  
Nonlinear Dynamical Systems ◽  
Initial Conditions ◽  
Random Number Generation ◽  
Chaotic Oscillator ◽  
Number Generation

The desirable properties exhibited in some nonlinear dynamical systems have many potential uses. These properties include sensitivity to initial conditions, wide bandwidth, and long-term aperiodicity, which lend themselves to applications such as random number generation, communication and audio ranging systems. Chaotic systems can be realized in electronics by using inexpensive and readily available parts. Many of these systems have been verified in electronics using nonpermanent prototyping at very low frequencies; however, this restricts the range of potential applications. In particular, random number generation (RNG) benefits from an increase in operation frequency, since it is proportional to the amount of bits that can be produced per second. This work looks specifically at the nonlinear element in the chaotic system and evaluates its frequency limitations in electronics. In practice, many of nonlinearities are difficult to implement in high speed electronics. In addition to this restriction, the use of complex feedback paths and large inductors prevents the miniaturization that is desirable for implementing chaotic circuits in other electronic systems. By carefully analyzing the fundamental dynamics that govern the chaotic system, these problems can be addressed. Presented in this work is the design and realization of a high frequency chaotic oscillator that exhibits complex and rich dynamics while using a compact footprint and low power consumption.

RECONFIGURABLE LOW POWER ARCHITECTURE FOR FAULT TOLERANT PSEUDO-RANDOM NUMBER GENERATION

2014 ◽  
Vol 23 (01) ◽  
pp. 1450002 ◽  
Author(s):  
NEMANJA SAVIĆ ◽  
MILE STOJČEV ◽  
TATJANA NIKOLIĆ ◽  
VLADIMIR PETROVIĆ ◽  
GORAN JOVANOVIĆ
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Random Number ◽  
Fault Tolerant ◽  
Design Solution ◽  
Ip Core ◽  
Fpga Architecture ◽  
Pseudo Random Number ◽  
Bicmos Technology

High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm2 area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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