scholarly journals Complementary Integrated Circuits Based on n-Type and p-Type Oxide Semiconductors for Applications Beyond Flat-Panel Displays

2019 ◽  
Vol 66 (2) ◽  
pp. 950-956 ◽  
Author(s):  
Yunpeng Li ◽  
Jiawei Zhang ◽  
Jin Yang ◽  
Yvzhuo Yuan ◽  
Zhenjia Hu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flat Panel Displays ◽  
Flat Panel ◽  
Oxide Semiconductors ◽  
P Type

Planarization of Deep Structures Using Self-Leveling Materials

2012 ◽  
Vol 2012 (1) ◽  
pp. 000079-000083
Author(s):  
Dongshun Bai ◽  
Michelle Fowler ◽  
Curtis Planje ◽  
Xie Shao
Keyword(s):  
Integrated Circuits ◽  
Microelectromechanical Systems ◽  
Flat Panel Displays ◽  
New Materials ◽  
Flat Panel ◽  
Light Emitting ◽  
Good Thermal Stability ◽  
Device Integration ◽  
Potential Applications ◽  
Processing Steps

To achieve device integration that will allow the manufacture of smaller, more functional, and more efficient microelectronics, the industry increasingly requires materials to fill and planarize devices with deep structures. Brewer Science has developed several new self-leveling materials to address these planarization needs. These newly developed materials are designed to be either temporary materials that can be removed after their use in processing steps or permanent materials that can stay in a device for its lifetime. These new materials can be applied easily by means of a spin-coating process. They are unique because they can fill and planarize high-aspect-ratio trenches and vias hundreds of microns deep. Some of the materials are photosensitive and can be patterned using photolithography. All of the photosensitive materials in this paper can be developed with industry-accepted solvents and some with an aqueous TMAH solution. Because of their good thermal stability, high transparency, and excellent planarization properties, these materials have potential applications for microelectromechanical systems (MEMS), 3-D integrated circuits, light-emitting diodes (LEDs), semiconductors, flat-panel displays, and related microelectronic and optoelectronic devices. This paper will discuss the properties of these new materials and will present the filling and leveling results obtained in several applications.

Use of Plasma Processing in Making Integrated Circuits and Flat-Panel Displays

MRS Bulletin ◽  
1996 ◽  
Vol 21 (8) ◽  
pp. 38-42 ◽  
Author(s):  
Richard A. Gottscho ◽  
Maria E. Barone ◽  
Joel M. Cook
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integrated Circuit ◽  
Plasma Processing ◽  
Pattern Transfer ◽  
Flat Panel Displays ◽  
Flat Panel Display ◽  
Large Area ◽  
Flat Panel ◽  
Microelectronic Devices

The ever-shrinking dimensions of microelectronic devices has mandated the use of plasma processing in integrated circuit (IC) factories worldwide. Today the plasma-processing industry has grown to over $3 billion in revenues per year, well in excess of predictions made only a few years ago. Plasma etching and deposition systems are also found throughout flat-panel-display (FPD) factories despite the much larger dimensions of thin-film transistors (TFTs) that are used to switch picture elements (pixels) on and off. Besides the use of plasma in etching and depositing thin films, other processes include the following: removal of photoresist remnants after development (descumming), stripping developed photoresist after pattern transfer (ashing), and passivating defects in polycrystalline material. Why are plasma processes so prevalent?In etching, plasmas are used for high-fidelity transfer of the photolithographically defined pattern that defines the device or circuit. More generally, plasma provides the means to taper sidewalls. In Si processing, the sidewalls must be nearly vertical to obtain high density integration and faster performance. However in making FPDs, sidewalls are tapered to obtain uniform step coverage and reduce shorting. In deposition, plasmas are used to enable processing at low temperature. For both etching and deposition, only plasma processing provides an economically viable means for processing large area substrates: 300 mm for Si and more than 550 × 650 mm for FPDs. It is the ability to scale uniform reactant generation to larger areas that sets plasma apart from beam-based processes that might otherwise offer the desired materials modifications. The nonequilibrium characteristics of plasma further distinguish this processing method. Energetic electrons break apart reactant precursors while ions bombard the surface anisotropically.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Evaluating Alternate Visualization Methods for Microsurgery: 2D and 3D Optical Microscopes and Flat-Panel Displays

2012 ◽  
Author(s):  
Michael Sackllah ◽  
Denny Yu ◽  
Charles Woolley ◽  
Steven Kasten ◽  
Thomas J. Armstrong
Keyword(s):  
Flat Panel Displays ◽  
Flat Panel ◽  
2D And 3D

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Two mask step polysilicon TFT technology for flat panel displays

1988 ◽  
Vol 24 (3) ◽  
pp. 156 ◽  
Author(s):  
B. Loisel ◽  
L. Haji ◽  
P. Sangouard ◽  
M. Sarret
Keyword(s):  
Flat Panel Displays ◽  
Flat Panel ◽  
Polysilicon Tft

Efficient organic manganese (II) bromide green-light-emitting diodes enabled by manipulating hole and electron transport layer

2021 ◽  
Author(s):  
Hyunsik Im ◽  
Atanu Jana ◽  
Vijaya Gopalan Sree ◽  
QIANKAI BA ◽  
Seong Chan Cho ◽  
...  
Keyword(s):  
Light Emitting Diodes ◽  
Green Light ◽  
Transport Layer ◽  
Lead Free ◽  
Electron Transport Layer ◽  
Flat Panel Displays ◽  
Flat Panel ◽  
Inorganic Hybrid ◽  
Light Emitting ◽  
Light Emitting Devices

Lead-free, non-toxic transition metal-based phosphorescent organic–inorganic hybrid (OIH) compounds are promising for next-generation flat-panel displays and solid-state light-emitting devices. In the present study, we fabricate highly efficient phosphorescent green-light-emitting diodes...

scholarly journals Development of IGZO TFTs and their applications to next‐generation flat‐panel displays

2010 ◽  
Vol 11 (4) ◽  
pp. 160-164 ◽  
Author(s):  
Hsing‐Hung Hsieh ◽  
Hsiung‐Hsing Lu ◽  
Hung‐Che Ting ◽  
Ching‐Sang Chuang ◽  
Chia‐Yu Chen ◽  
...  
Keyword(s):  
Flat Panel Displays ◽  
Next Generation ◽  
Flat Panel

Ultra barrier flexible substrates for flat panel displays

Displays ◽  
2001 ◽  
Vol 22 (2) ◽  
pp. 65-69 ◽  
Author(s):  
P.E Burrows ◽  
G.L Graff ◽  
M.E Gross ◽  
P.M Martin ◽  
M.K Shi ◽  
...  
Keyword(s):  
Flexible Substrates ◽  
Flat Panel Displays ◽  
Flat Panel
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