Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy

2016 ◽  
Vol 63 (8) ◽  
pp. 3165-3170 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Gate Bias ◽  
Nonlinear Dielectric ◽  
Carrier Redistribution

Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Cross Section ◽  
Measurement System ◽  
Higher Order ◽  
Depletion Layer ◽  
Gate Bias ◽  
Power Mosfet ◽  
Nonlinear Dielectric ◽  
Voltage Dependent ◽  
Carrier Redistribution ◽  
Source Voltage

Abstract Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Two-Dimensional Local Deep-Level Transient Spectroscopy Imaging Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2016 ◽  
Author(s):  
N. Chinone ◽  
Y. Cho ◽  
R. Kosugi ◽  
Y. Tanaka ◽  
S. Harada ◽  
...  
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Higher Order ◽  
Trap Density ◽  
New Technique ◽  
Two Dimensional ◽  
Nonlinear Dielectric ◽  
Annealing Conditions ◽  
Transient Spectroscopy ◽  
A New Technique

Abstract A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique. SiCVSiC structure samples with different post oxidation annealing conditions were measured. We observed that the local DLTS signal decreases with post oxidation annealing (POA), which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiCVSiC interface.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Tunable microwave mixing in nonlinear dielectric thin films of SrTiO3 and Sr0.5Ba0.5TiO3

1995 ◽  
Vol 31 (21) ◽  
pp. 1814-1815 ◽  
Author(s):  
A.T. Findikoglu ◽  
D.W. Reagor ◽  
Q.X. Jia ◽  
X.D. Wu
Keyword(s):  
Thin Films ◽  
Dielectric Thin Films ◽  
Nonlinear Dielectric ◽  
Tunable Microwave

Demonstration of the enhancement of gate bias and ionic strength in electric-double-layer field-effect-transistor biosensors

2021 ◽  
Vol 334 ◽  
pp. 129567
Author(s):  
Chang-Run Wu ◽  
Shin-Li Wang ◽  
Po-Hsuan Chen ◽  
Yu-Lin Wang ◽  
Yu-Rong Wang ◽  
...  
Keyword(s):  
Ionic Strength ◽  
Double Layer ◽  
Electric Double Layer ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Bias ◽  
Effect Transistor
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