Abstract
The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-field around the guard rings on a WBG device. However, planar power package, such as double-sided and power flip-chip device packaging could be a problem where the close distance between the topside of the power device and conducting plane may negatively affect the E-field distribution of the guard rings, which in turn lowers the reverse blocking capability of the WBG power device and increases leakage current creating greater on-state power loss, or even early break down. Few works have shown the Electric field distribution in embedded power modules. Therefore, a more detailed investigation and possible solution is needed for the proliferation of double-sided power packages.
To investigate this packaging problem simulations were performed in Sentaurus TCAD and COMSOL based on the device physics and package geometries. Guard ring structures in 1.2kV and 10kV SiC Schottky Barrier Diode (SBD) were built and simulated in various double-sided package geometries, together with the thermal and mechanical evaluation of the package, to observe the influence on the E-field distribution in and out the WBG device. Different double-sided package structures were evaluated and a guideline (spacing/pad size/etc.) summarized for double-sided design. Moreover, a new bevel edge termination method was evaluated for double-sided WBG power semiconductor devices.
Experimental reverse blocking test results will be reported in various temperature (from 25°C to 175°C) to verify the function of the package. The tests are on 1200V/50A SiC SBD (Schottky Barrier Diode) from Global Power Technology, which has double-sided Ag on both sides.
Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode With Gated Edge Termination on 200-mm Silicon Substrate