Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

2015 ◽  
Vol 62 (2) ◽  
pp. 673-679 ◽  
Author(s):  
Yong Jun Kim ◽  
Woo Young Choi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Field-programmable gate arrays in a low power vision system

2021 ◽  
Vol 90 ◽  
pp. 106996
Author(s):  
Suresh P. ◽  
Saravanakumar U. ◽  
Celestine Iwendi ◽  
Senthilkumar Mohan ◽  
Gautam Srivastava
Keyword(s):  
Low Power ◽  
Vision System ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 353 ◽  
Author(s):  
Anees Ullah ◽  
Ali Zahir ◽  
Noaman A. Khan ◽  
Waleed Ahmad ◽  
Alexis Ramos ◽  
...  
Keyword(s):  
Resource Utilization ◽  
High Speed ◽  
State Of The Art ◽  
Field Programmable Gate Arrays ◽  
Partial Reconfiguration ◽  
Gate Arrays ◽  
Content Addressable Memories ◽  
Field Programmable ◽  
Programmable Gate Arrays

Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.

Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays

2007 ◽  
Vol 55 (7) ◽  
pp. 3526-3535 ◽  
Author(s):  
David Halupka ◽  
Alireza Seyed Rabi ◽  
Parham Aarabi ◽  
Ali Sheikholeslami
Keyword(s):  
Low Power ◽  
Speech Enhancement ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

USING FIELD-PROGRAMMABLE GATE ARRAYS FOR HIGH-SPEED REAL-TIME SIMULATION

2010 ◽  
Vol 01 (01) ◽  
pp. 99-115 ◽  
Author(s):  
ROY CROSBIE
Keyword(s):  
Real Time ◽  
High Speed ◽  
Digital Signal ◽  
Field Programmable Gate Arrays ◽  
Electronic Systems ◽  
Real Time Simulation ◽  
Gate Arrays ◽  
Time Simulation ◽  
Field Programmable ◽  
Programmable Gate Arrays

Some applications of real-time simulation now require frame times that are shorter in duration than can be delivered by traditional methods such as real-time versions of Linux (RT-Linux). RT-Linux can be satisfactory for frames as short as 10μS, but there is now a need, for example in the simulation of power-electronic systems, for frame times as short as 1 μS or even less. Techniques based on the interfacing of digital signal processors (DSPs) to a Windows PC have achieved a 2 μS frame time for a typical power electronics application and less than 1 μS is shown to be possible using field-programmable gate arrays (FPGAs). Combining these high-speed techniques with simulations of the rest of the system necessitates the use of multi-rate techniques. Software tools, interfacing issues, and system architecture for a high-speed, real-time, distributed, multi-rate (HRDM) simulator are discussed.

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs

2017 ◽  
Vol 27 (01) ◽  
pp. 1850002
Author(s):  
Burhan Khurshid
Keyword(s):  
High Speed ◽  
Field Programmable Gate Arrays ◽  
Prior Work ◽  
Power Performance ◽  
Output Node ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Generalized parallel counters (GPCs) are frequently used to construct high speed compressor trees on field programmable gate arrays (FPGAs). The introduction of fast carry-chain in FPGAs has greatly improved the performance of these elements. Evidently, a large number of GPCs have been proposed in literature that use a combination of look-up tables (LUTs) and carry-chains. In this paper, we take an alternate approach and try to eliminate the carry-chain from the GPC structure. We present a heuristic that aims at synthesizing GPCs on FPGAS using only the general LUT fabric. The resultant GPCs are then easily pipelined by placing registers at the output node of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry-chain from the GPC structure with an increase in LUT count in some GPCs. Experimentation using Xilinx FPGAs shows that filter systems constructed using our GPCs show an improvement in speed and power performance and a comparable area performance.

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