Performance Improvement Versus CPW and Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology

2012 ◽  
Vol 59 (5) ◽  
pp. 1279-1285 ◽  
Author(s):  
Xiao-Lan Tang ◽  
Anne-Laure Franc ◽  
Emmanuel Pistono ◽  
Alexandre Siligaris ◽  
Pierre Vincent ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Slow Wave ◽  
Cmos Technology ◽  
Distribution Analysis ◽  
Loss Distribution ◽  
Soi Cmos

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

2012 ◽  
Author(s):  
John Bulzacchelli ◽  
Troy Beukema ◽  
Daniel Storaska ◽  
Ping-Hsuan Hsieh ◽  
Sergey Rylov ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Serial Link ◽  
Serial Link Transceiver ◽  
Soi Cmos

scholarly journals Resonant Body Transistors in IBM's 32 nm SOI CMOS Technology

2014 ◽  
Vol 23 (3) ◽  
pp. 636-650 ◽  
Author(s):  
Radhika Marathe ◽  
Bichoy Bahr ◽  
Wentao Wang ◽  
Zohaib Mahmood ◽  
Luca Daniel ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Soi Cmos

Slow-wave high-Q coplanar striplines in CMOS technology and their RLCG model

2012 ◽  
Vol 54 (3) ◽  
pp. 650-654 ◽  
Author(s):  
M. Abdel Aziz ◽  
F. Podevin ◽  
A. M. E. Safwat ◽  
A. Vilcot ◽  
P. Ferrari
Keyword(s):  
Slow Wave ◽  
Cmos Technology ◽  
High Q

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

A 0.35-V inductorless DC-DC converter using non-SOI CMOS technology

2016 ◽  
Author(s):  
Haidong Sun ◽  
Sho Hoshino ◽  
Hirokazu Yoshizawa ◽  
Fumiyasu Utsunomiya ◽  
Minoru Sudo
Keyword(s):  
Cmos Technology ◽  
Soi Cmos
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