Single-Electron-Based Flexible Multivalued Exclusive-or Logic Gate

2009 ◽  
Vol 56 (5) ◽  
pp. 1048-1055 ◽  
Author(s):  
Sang-Jin Kim ◽  
Chang-Keun Lee ◽  
Rae-Sik Chung ◽  
Eun-Sil Park ◽  
Seung-Jun Shin ◽  
...  
Keyword(s):  
Logic Gate ◽  
Single Electron ◽  
Exclusive Or ◽  
Or Logic Gate

Single Electron-based Flexible Multi-valued Exclusive-OR Logic Gate

2007 ◽  
Author(s):  
S. J. Kim ◽  
C. K. Lee ◽  
R. S. Chung ◽  
M. S. Kim ◽  
E. S. Park ◽  
...  
Keyword(s):  
Logic Gate ◽  
Single Electron ◽  
Exclusive Or ◽  
Or Logic Gate

Genetic Evolution for the Development of Robust Artificial Neural Network Logic Gates

2009 ◽  
Author(s):  
Anthony M. Roy ◽  
Erik K. Antonsson ◽  
Andrew A. Shapiro
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Design Methods ◽  
Neural Net ◽  
C Programs ◽  
Artificial Neural Net ◽  
Classical Design ◽  
Artificial Neural ◽  
Exclusive Or ◽  
Or Logic Gate

Control tasks involving dramatic non-linearities, such as decision making, can be challenging for classical design methods. However, autonomous stochastic design methods have proved effective. In particular, Genetic Algorithms (GA) that create phenotypes by the application of genotypes comprising rules are robust and highly scalable. Such encodings are useful for complex applications such as artificial neural net design. This paper outlines an evolutionary algorithm that creates C++ programs which in turn create Artificial Neural Networks (ANNs) that can functionally perform as an exclusive-OR logic gate. Furthermore, the GAs are able to create scalable ANNs robust enough to feature redundancies that allow the network to function despite internal failures.

scholarly journals High Performance Energy Efficient Computation Elements of Processing Unit

2019 ◽  
Vol 9 (2) ◽  
pp. 2450-2455
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Logic Gate ◽  
Processing Unit ◽  
Efficient Computation ◽  
Quartus Ii ◽  
Efficient Processing ◽  
Exclusive Or ◽  
Design Logic

in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

Dynamic exclusive-OR gate based on gate-induced Si island single-electron transistor

2002 ◽  
Vol 38 (11) ◽  
pp. 527 ◽  
Author(s):  
Dae Hwan Kim ◽  
Kyung Rok Kim ◽  
Suk-Kang Sung ◽  
Jong Duk Lee ◽  
Byung-Gook Park
Keyword(s):  
Single Electron ◽  
Single Electron Transistor ◽  
Exclusive Or ◽  
Or Gate
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