Two-Dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET With Electrically Induced S/D Extensions

2005 ◽  
Vol 52 (7) ◽  
pp. 1568-1575 ◽  
Author(s):  
M.J. Kumar ◽  
A.A. Orouji
Keyword(s):  
Threshold Voltage ◽  
Two Dimensional ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Threshold Voltage Model

scholarly journals Analysis of Mismatching on the Analog Characteristics of GC SOI MOSFETs

2018 ◽  
Vol 13 (3) ◽  
pp. 1-8
Author(s):  
Camila Alves ◽  
Denis Flandre ◽  
Michelly De Souza
Keyword(s):  
Threshold Voltage ◽  
Voltage Gain ◽  
Two Dimensional ◽  
Subthreshold Slope ◽  
Electrical Measurements ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Basic Parameters ◽  
Output Conductance ◽  
Analog Parameters

This paper presents an evaluation of mismatching impact on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. This study is carried out by means of electrical measurements and two-dimensional numerical simulations, comparing GC to uniformly doped transistors. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Sign in / Sign up

Export Citation Format

Share Document