On multi-cycle path support in model based high-level synthesis

2014 ◽  
Author(s):  
Chandan Karfa ◽  
Sheetal Jain
Keyword(s):  
High Level Synthesis ◽  
Model Based ◽  
High Level ◽  
Cycle Path

scholarly journals A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA

2020 ◽  
Vol 12 (3) ◽  
pp. 80-84
Author(s):  
Syed Jahanzeb Hussain Pirzada ◽  
◽  
Abid Murtaza ◽  
Tongge Xu ◽  
Liu Jianwei
Keyword(s):  
Rapid Prototyping ◽  
Hardware Implementation ◽  
Digital Systems ◽  
System Level ◽  
High Level Synthesis ◽  
Time To Market ◽  
Model Based ◽  
Stage Of Development ◽  
Trade Offs ◽  
High Level

The digital design methodologies are evolving with the increase of digital systems utilization in daily life. The Model Based Design (MBD) methodology provides a unique methodology for design and implementation of digital systems on Field Programmable Gate Array (FPGA). Recently, a lot of research effort has been put to exploit new methodologies for designing and prototyping of digital systems on FPGA. The FPGA hardware provides prototyping which provides means of verifying your design at an early stage of development cycle. This helps to evaluate design trade-offs by testing the design in real-time on hardware. Making prototypes is a common practice in research-oriented projects. However, it requires excess development time which increases time to market of the product. This paper illustrates the use of reconfigurable MBD for rapid prototyping of digital systems on Microsemi ACTEL FPGAs for improving the design-cycle and time-to-market of a product. The model is simulated to verify the functionality of the design at system-level and a high-level code is generated from the MBD toolset embedded in MATLAB for hardware implementation. Then, a High-Level Synthesis (HLS) is performed on the generated code which converts this high-level code into Verilog-HDL suitable for hardware implementation on FPGA. Hence, this work presents a methodology and its analysis for design of digital system using high-level synthesis on Microsemi ACTEL FPGA.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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