Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE

Anastasios N. Bikos; Nicolas Sklavos

doi:10.1109/tdsc.2016.2620437

Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE

IEEE Transactions on Dependable and Secure Computing ◽

10.1109/tdsc.2016.2620437 ◽

2018 ◽

Vol 15 (5) ◽

pp. 729-741 ◽

Cited By ~ 5

Author(s):

Anastasios N. Bikos ◽

Nicolas Sklavos

Keyword(s):

High Speed ◽

Architecture Design ◽

4G Lte ◽

Area Efficient

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Real-time area efficient and high speed architecture design of Viterbi decoder

2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB) ◽

10.1109/aeeicb.2016.7538282 ◽

2016 ◽

Cited By ~ 1

Author(s):

Amitava Middya ◽

Anindya S. Dhar

Keyword(s):

Real Time ◽

High Speed ◽

Architecture Design ◽

Viterbi Decoder ◽

Area Efficient

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

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Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2019.8754423 ◽

2019 ◽

Author(s):

Diptesh Datta ◽

Piyush Dewangan ◽

Neelam Surana ◽

Joycee Mekie

Keyword(s):

High Speed ◽

Content Addressable Memory ◽

Ternary Content Addressable Memory ◽

Area Efficient

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Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Circuits Systems and Signal Processing ◽

10.1007/s00034-021-01738-1 ◽

2021 ◽

Author(s):

Suresh Mopuri ◽

Amit Acharyya

Keyword(s):

High Speed ◽

Design Methodology ◽

Low Complexity ◽

Architecture Design ◽

Square Root

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Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Materials Today Proceedings ◽

10.1016/j.matpr.2020.07.677 ◽

2020 ◽

Author(s):

A. Arunkumar Gudivada ◽

K. Jayaram Kumar ◽

Srinivasa Rao Jajula ◽

Durga Prasad Siddani ◽

Praveen Kumar Poola ◽

...

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

High Speed ◽

Quantum Dot Cellular Automata ◽

Wallace Tree ◽

Wallace Tree Multiplier ◽

Area Efficient

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High-speed area-efficient recursive DFT/IDFT architectures

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328757 ◽

2004 ◽

Author(s):

Lan-Da Van ◽

Chih-Chyau Yang

Keyword(s):

High Speed ◽

Area Efficient

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Information Flow Analysis and Software Architecture Design for the Vehicle Control System in a High-Speed Maglev Transportation System

CICTP 2016 ◽

10.1061/9780784479896.093 ◽

2016 ◽

Cited By ~ 6

Author(s):

Yijun Chen ◽

Huahua Zhao ◽

Zhiming Liao ◽

Yi Yu

Keyword(s):

Control System ◽

Software Architecture ◽

Information Flow ◽

High Speed ◽

Flow Analysis ◽

Transportation System ◽

Vehicle Control ◽

Architecture Design ◽

Information Flow Analysis ◽

Maglev Transportation System

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High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378152 ◽

2007 ◽

Cited By ~ 9

Author(s):

A. Abdelgawad ◽

Magdy Bayoumi

Keyword(s):

High Speed ◽

Digital Signal ◽

Area Efficient

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FPGA Acceleration Architecture Design and Implementation of Satellite Ground Fusion High-Speed Transmission Link

2021 IEEE Asia-Pacific Conference on Image Processing, Electronics and Computers (IPEC) ◽

10.1109/ipec51340.2021.9421091 ◽

2021 ◽

Author(s):

Yilong Li ◽

Yun Liu ◽

Zhiqun Song ◽

Ruiliang Song ◽

Haipeng Zhang ◽

...

Keyword(s):

High Speed ◽

Architecture Design ◽

Design And Implementation ◽

Transmission Link ◽

Fpga Acceleration

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A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8333237 ◽

2017 ◽

Author(s):

Junxi Chen ◽

Shengqun Zheng ◽

Kai Sheng ◽

Weixin Gai ◽

Jianhua Feng

Keyword(s):

High Resolution ◽

Low Power ◽

High Speed ◽

Calibration Technique ◽

Wide Range ◽

Area Efficient

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Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE

Real-time area efficient and high speed architecture design of Viterbi decoder

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

High-speed area-efficient recursive DFT/IDFT architectures

Information Flow Analysis and Software Architecture Design for the Vehicle Control System in a High-Speed Maglev Transportation System

High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

FPGA Acceleration Architecture Design and Implementation of Satellite Ground Fusion High-Speed Transmission Link

A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata