Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation

2011 ◽  
Vol 8 (5) ◽  
pp. 756-769 ◽  
Author(s):  
Yu Wang ◽  
Hong Luo ◽  
Ku He ◽  
Rong Luo ◽  
Huazhong Yang ◽  
...  
Keyword(s):  
Performance Degradation ◽  
Circuit Performance ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
The Impact

scholarly journals Does Prenatal Stress Management Enhance Maternal And Fetal Outcomes?

2016 ◽  
Vol 12 (27) ◽  
pp. 129
Author(s):  
Ghada Mohammad Abu Shosha
Keyword(s):  
Pregnant Women ◽  
Stress Management ◽  
Stress Reduction ◽  
Maternal Stress ◽  
Rapid Change ◽  
Fetal Outcomes ◽  
Reduction Techniques ◽  
Antenatal Stress ◽  
Fetal Organs ◽  
The Impact

Background: Antenatal period is a time of rapid change during which fetal organs are vulnerable to various stressors. Studies have suggested that psychosocial stressors during pregnancy could adversely influence physical and behavioral outcomes of the infant. Aim: This paper aimed to discusses the importance of antenatal stress assessment and management on both mothers' and infants' health status. Method: This review aggregated evidence from various studies that examined the impact of maternal stress management and its outcomes on pregnant women and their infants. Results: Maternal stress is generally associated with unpleasant fetal outcomes. The use of stress reduction techniques was approved to reduce psychological stress in pregnant women. Conclusion: Ongoing assessment of antenatal stress using a standardized process promotes proper stress handling strategy.

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

Cache Leakage Reduction Techniques for Hybrid SPM-Cache Architectures

2020 ◽  
pp. 2150008
Author(s):  
Hao Wen ◽  
Wei Zhang
Keyword(s):  
Large Fraction ◽  
Hybrid Architecture ◽  
Total Energy Consumption ◽  
Access Frequency ◽  
Reduction Techniques ◽  
Cache Architecture ◽  
Scratch Pad Memory ◽  
Significant Performance ◽  
Power Mode ◽  
The Impact

Leakage energy has become an increasingly large fraction of total energy consumption, making it important to reduce leakage energy for improving the overall energy efficiency for embedded processors. In this paper, we explore how to reduce the cache leakage energy efficiently in a hybrid Scratch-Pad Memory (SPM) and cache architecture. Different from stand-alone cache, since the frequently used data may be allocated to the SPM for rapid retrieval in the hybrid architecture, the access frequency to the cache is reduced. It is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated VDD (HDG) technique, which can adaptively exploit both short and long idle intervals of cache accesses to minimize leakage energy with insignificant performance overhead. In addition, we discussed the impact of cache size on the idle intervals of accesses, which will affect the efficiency of leakage management methods that exploit the idle intervals to reduce leakage energy.

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