Byte and Modulo Addressable Parallel Memory Architecture for Video Coding

J.K. Tanskanen; T. Sihvo; J. Niittylahti

doi:10.1109/tcsvt.2004.835148

Byte and Modulo Addressable Parallel Memory Architecture for Video Coding

IEEE Transactions on Circuits and Systems for Video Technology ◽

10.1109/tcsvt.2004.835148 ◽

2004 ◽

Vol 14 (11) ◽

pp. 1270-1276 ◽

Cited By ~ 15

Author(s):

J.K. Tanskanen ◽

T. Sihvo ◽

J. Niittylahti

Keyword(s):

Video Coding ◽

Memory Architecture ◽

Parallel Memory

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A parallel memory architecture for video coding

Journal of Zhejiang University SCIENCE A ◽

10.1631/jzus.a0820052 ◽

2008 ◽

Vol 9 (12) ◽

pp. 1644-1655 ◽

Cited By ~ 4

Author(s):

Jian-ying Peng ◽

Xiao-lang Yan ◽

De-xian Li ◽

Li-zhong Chen

Keyword(s):

Video Coding ◽

Memory Architecture ◽

Parallel Memory

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Enhanced configurable parallel memory architecture

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115348 ◽

2003 ◽

Author(s):

J. Vanne ◽

E. Aho ◽

K. Kuusilinna ◽

T. Hamalainen

Keyword(s):

Memory Architecture ◽

Parallel Memory

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Configurable parallel memory architecture for multimedia computers

Journal of Systems Architecture ◽

10.1016/s1383-7621(02)00059-0 ◽

2002 ◽

Vol 47 (14-15) ◽

pp. 1089-1115 ◽

Cited By ~ 2

Author(s):

Kimmo Kuusilinna ◽

Jarno Tanskanen ◽

Timo Hämäläinen ◽

Jarkko Niittylahti

Keyword(s):

Memory Architecture ◽

Parallel Memory

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Video-Active RAM: A processor-in-memory architecture for video coding applications

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5538024 ◽

2010 ◽

Cited By ~ 1

Author(s):

Mohammed Sayed ◽

Wael Badawy ◽

Graham Jullien

Keyword(s):

Video Coding ◽

Memory Architecture

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Application specific parallel memory architecture for software defined radio

2011 IEEE 3rd International Conference on Communication Software and Networks ◽

10.1109/iccsn.2011.6013745 ◽

2011 ◽

Author(s):

Botao Zhang ◽

Hengzhu Liu ◽

Shixian Wang ◽

Dongpei Liu

Keyword(s):

Software Defined Radio ◽

Memory Architecture ◽

Parallel Memory ◽

Application Specific

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Scalable Parallel Memory Architectures for Video Coding

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1023/b:vlsi.0000040428.04740.fe ◽

2004 ◽

Vol 38 (2) ◽

pp. 173-199 ◽

Cited By ~ 11

Author(s):

Jarno K. Tanskanen ◽

Jarkko T. Niittylahti

Keyword(s):

Video Coding ◽

Parallel Memory ◽

Memory Architectures

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dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date2014.033 ◽

2014 ◽

Cited By ~ 5

Author(s):

Felipe Sampaio ◽

Muhammad Shafique ◽

Bruno Zatt ◽

Sergio Bampi ◽

Jorg Henkel

Keyword(s):

Video Coding ◽

Energy Efficient ◽

High Efficiency ◽

Memory Architecture ◽

Next Generation ◽

High Efficiency Video Coding ◽

Video Memory

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Parallel Memory Architecture for Arbitrary Stride Accesses

2006 IEEE Design and Diagnostics of Electronic Circuits and systems ◽

10.1109/ddecs.2006.1649572 ◽

2006 ◽

Cited By ~ 4

Author(s):

E. Aho ◽

J. Vanne ◽

T.D. Hamalainen

Keyword(s):

Memory Architecture ◽

Parallel Memory

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An on-chip parallel memory architecture for a stereo vision system

2010 17th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2010.5724557 ◽

2010 ◽

Cited By ~ 2

Author(s):

Andy Motten ◽

Luc Claesen

Keyword(s):

Stereo Vision ◽

Vision System ◽

Memory Architecture ◽

Parallel Memory ◽

Stereo Vision System ◽

On Chip

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Parallel Memory Architecture for Elliptic Curve Cryptography over % MathType!Translator!2!1!AMS LaTeX.tdl!TeX -- AMS-LaTeX! % MathType!MTEF!2!1!+- % feaaeaart1ev0aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbbjxAHX % garmWu51MyVXgatuuDJXwAK1uy0HwmaeHbfv3ySLgzG0uy0Hgip5wz % aebbnrfifHhDYfgasaacH8qrps0lbbf9q8WrFfeuY-Hhbbf9v8qqaq % Fr0xc9pk0xbba9q8WqFfea0-yr0RYxir-Jbba9q8aq0-yq-He9q8qq % Q8frFve9Fve9Ff0dmeaabaqaciGacaGaaeqabaWaaeWaeaaakeaatu % uDJXwAK1uy0HMmaeXbfv3ySLgzG0uy0HgiuD3BaGqbaiab-zi8hjab % -vi8gnaabmaabaGaamiCaaGaayjkaiaawMcaaaaa!4834! $$ \mathbb{G}\mathbb{F}{\left( p \right)} $$ Aimed at Efficient FPGA Implementation

Journal of Signal Processing Systems ◽

10.1007/s11265-007-0135-9 ◽

2007 ◽

Vol 51 (1) ◽

pp. 39-55 ◽

Cited By ~ 4

Author(s):

Ralf Laue ◽

Sorin A. Huss

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

Fpga Implementation ◽

Memory Architecture ◽

Parallel Memory

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