A new RISC processor architecture for MPEG-2 decoding

K. Yamada; M. Kojima; T. Shimizu; F. Sato; T. Mizuno

doi:10.1109/tce.2002.1010104

A new RISC processor architecture for MPEG-2 decoding

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2002.1010104 ◽

2002 ◽

Vol 48 (1) ◽

pp. 143-150 ◽

Cited By ~ 2

Author(s):

K. Yamada ◽

M. Kojima ◽

T. Shimizu ◽

F. Sato ◽

T. Mizuno

Keyword(s):

Processor Architecture ◽

Risc Processor

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An IBM second generation RISC processor architecture

Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage ◽

10.1109/cmpcon.1990.63668 ◽

2002 ◽

Author(s):

R.D. Groves ◽

R. Oehler

Keyword(s):

Second Generation ◽

Processor Architecture ◽

Risc Processor

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A RISC processor architecture with a versatile stack system

ACM SIGARCH Computer Architecture News ◽

10.1145/165660.165673 ◽

1993 ◽

Vol 21 (5) ◽

pp. 63-70 ◽

Cited By ~ 3

Author(s):

Claus Aßmann

Keyword(s):

Processor Architecture ◽

Risc Processor

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SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture

2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2016.7760804 ◽

2016 ◽

Cited By ~ 2

Author(s):

Ahmed S. Eissa ◽

Mahmoud A. Elmohr ◽

Mostafa A. Saleh ◽

Khaled E. Ahmed ◽

Mohammed M. Farag

Keyword(s):

Instruction Set ◽

Processor Architecture ◽

Risc Processor ◽

Instruction Set Extension

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An IBM second generation RISC processor architecture

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1989.63343 ◽

2003 ◽

Cited By ~ 5

Author(s):

R.D. Groves ◽

R. Oehler

Keyword(s):

Second Generation ◽

Processor Architecture ◽

Risc Processor

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DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.4.14864 ◽

2018 ◽

Vol 6 (4) ◽

pp. 38

Author(s):

S. M. BHAGAT ◽

S. U. BHANDARI ◽

◽

Keyword(s):

Risc Processor

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Customising a processor architecture for multimedia applications

Electronic Systems and Software ◽

10.1049/ess:20030406 ◽

2003 ◽

Vol 1 (4) ◽

pp. 29-33 ◽

Cited By ~ 1

Author(s):

H. Eichel

Keyword(s):

Multimedia Applications ◽

Processor Architecture

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FPGA prototyping of a RISC processor core for embedded applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924027 ◽

2001 ◽

Vol 9 (2) ◽

pp. 241-250 ◽

Cited By ~ 36

Author(s):

M. Gschwind ◽

V. Salapura ◽

D. Maurer

Keyword(s):

Processor Core ◽

Risc Processor ◽

Embedded Applications

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Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets

2020 16th International Conference on Control, Automation, Robotics and Vision (ICARCV) ◽

10.1109/icarcv50220.2020.9305402 ◽

2020 ◽

Author(s):

Maciej Kopczynski ◽

Tomasz Grzes

Keyword(s):

Rough Set ◽

Processor Architecture

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Design of Efficient Dynamic Scheduling of RISC Processor Instructions

2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) ◽

10.1109/iemcon51383.2020.9284902 ◽

2020 ◽

Author(s):

Anudeep Bonasu ◽

Sushanth Reddy Karmunchi ◽

Nan Wang

Keyword(s):

Dynamic Scheduling ◽

Risc Processor

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Towards Efficient Superconducting Quantum Processor Architecture Design

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems ◽

10.1145/3373376.3378500 ◽

2020 ◽

Cited By ~ 4

Author(s):

Gushu Li ◽

Yufei Ding ◽

Yuan Xie

Keyword(s):

Architecture Design ◽

Processor Architecture ◽

Quantum Processor

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