Booting Time Minimization for Real-Time Embedded Systems with Non-Volatile Memory

2014 ◽  
Vol 63 (4) ◽  
pp. 847-859 ◽  
Author(s):  
Che-Wei Chang ◽  
Chuan-Yue Yang ◽  
Yuan-Hao Chang ◽  
Tei-Wei Kuo
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Non Volatile Memory ◽  
Time Minimization ◽  
Volatile Memory

scholarly journals NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1304
Author(s):  
Thomas Haywood Dadzie ◽  
Jiwon Lee ◽  
Jihye Kim ◽  
Hyunok Oh
Keyword(s):  
Embedded Systems ◽  
Block Cipher ◽  
High Energy ◽  
Main Memory ◽  
Security Issue ◽  
Avalanche Effect ◽  
Hybrid Encryption ◽  
Short Period ◽  
Non Volatile Memory ◽  
Volatile Memory

The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.

Providing Security of Vital Data for Conventional Microcontroller Applications

2015 ◽  
Vol 789-790 ◽  
pp. 1059-1066
Author(s):  
Bayram Akdemir ◽  
Hasan Üzülmez
Keyword(s):  
Real Time ◽  
Power Loss ◽  
Gray Code ◽  
The Other ◽  
Reading Problem ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High Flexibility ◽  
Almost All

Microcontrollers are widely used in industrial world, and almost all kind of devices were based on microcontroller to achieve high flexibility and abilities. All microcontrollers have nonvolatile and volatile memories to execute the software. During the running, microcontroller calculates many variables and records them to any non-volatile memory to use later. After re-energizing, microcontroller takes the data calculated before the power off and executes the program. In case of any electrical writing error or any power loss during the writing procedure, un-written memory blocks or any un-written data leads to malfunctions. Proposed method uses a gray code based signed two memory blocks to secure the memory reserved for data. Microcontroller uses these memory blocks in alternately. Even if microcontroller has no any real-time ability, gray code provides a guarantee which block is written in last. For every re-starting microcontroller dos not lose the data. In case of any reading problem during the starting, microcontroller has two chances to decide the action. One is to start with default values and the other is to start with the previous data. This study is tested at elevator applications not to lose position and vital values.

Power-Fail Detection and Data Storage Design for Control System

2011 ◽  
Vol 383-390 ◽  
pp. 4121-4124
Author(s):  
Liu Min Wang ◽  
Bo Mo
Keyword(s):  
Control System ◽  
Real Time ◽  
Data Storage ◽  
Circuit Design ◽  
Real Time Clock ◽  
Design For Control ◽  
Non Volatile Memory ◽  
System Information ◽  
Volatile Memory ◽  
Information Integrity

The purpose of power-fail protection design is to ensure the certainty and integrity of system information. The key point of design includes: the signals of power-fail detection and data treatm- ent; real-time clock circuit design which is synchronous with the system or as a mark of time; using non-volatile memory (such as FRAM) or using battery backup to maintain trade volatile memory (eg RAM) power to ensure the information integrity and non-volatile storage when the power is removed.

scholarly journals Real-Time Analytics, Hybrid Transactional/Analytical Processing, In-Memory Data Management, and Non-Volatile Memory

2021 ◽  
Vol 33 (3) ◽  
pp. 171-198
Author(s):  
Sergey Dmitrievich Kuznetsov ◽  
Pavel Evgenievich Velikhov ◽  
Qiang Fu
Keyword(s):  
Data Management ◽  
Real Time ◽  
Concurrency Control ◽  
Just In Time ◽  
Non Volatile Memory ◽  
Analytical Processing ◽  
Volatile Memory ◽  
The One ◽  
New Generation ◽  
Operational Data

These days, real-time analytics is one of the most often used notions in the world of databases. Broadly, this term means very fast analytics over very fresh data. Usually the term comes together with other popular terms, hybrid transactional/analytical processing (HTAP) and in-memory data processing. The reason is that the simplest way to provide fresh operational data for analysis is to combine in one system both transactional and analytical processing. The most effective way to provide fast transactional and analytical processing is to store an entire database in memory. So on the one hand, these three terms are related but on the other hand, each of them has its own right to life. In this paper, we provide an overview of several in-memory data management systems that are not HTAP systems. Some of them are purely transactional, some are purely analytical, and some support real-time analytics. Then we overview nine in-memory HTAP DBMSs, some of which don't support real-time analytics. Existing real-time in-memory HTAP DBMSs have very diverse and interesting architectures although they use a number of common approaches: multiversion concurrency control, multicore parallelization, advanced query optimization, just in time compilation, etc. Additionally, we are interested whether these systems use non-volatile memory, and, if yes, in what manner. We conclude that an emergence of new generation of NVM will greatly stimulate its use in in-memory HTAP systems.

scholarly journals HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-23
Author(s):  
Mario Günzel ◽  
Christian Hakert ◽  
Kuan-Hsun Chen ◽  
Jian-Jia Chen
Keyword(s):  
Energy Consumption ◽  
Real Time ◽  
Shared Memory ◽  
Computing System ◽  
Dynamic Power Management ◽  
Real Time System ◽  
Extensive Evaluation ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Architectures

Dynamic power management (DPM) reduces the power consumption of a computing system when it idles, by switching the system into a low power state for hibernation. When all processors in the system share the same component, e.g., a shared memory, powering off this component during hibernation is only possible when all processors idle at the same time. For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced. In this work, we consider real-time systems with hybrid shared-memory architectures, which consist of shared volatile memory (VM) and non-volatile memory (NVM). Energy-efficient execution is achieved by applying DPM to turn off all memories during the hibernation mode. Towards this, we first explore the hybrid memory architectures and suggest a task model, which features configurable hibernation overheads. We propose a multi-processor procrastination algorithm (HEART), based on partitioned earliest-deadline-first (pEDF) scheduling. Our algorithm facilitates reducing the energy consumption by actively enlarging the hibernation time. It enforces all processors to idle simultaneously without violating the schedulability condition, such that the system can enter the hibernation state, where shared memories are turned off. Throughout extensive evaluation of HEART, we demonstrate (1) the increase in potential hibernation time, respectively the decrease in energy consumption, and (2) that our algorithm is not only more general but also has better performance than the state of the art with respect to energy efficiency in most cases.

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory
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