Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors

Christian Fensch; Nick Barrow-Williams; Robert D. Mullins; Simon Moore

doi:10.1109/tc.2012.52

Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors

IEEE Transactions on Computers ◽

10.1109/tc.2012.52 ◽

2013 ◽

Vol 62 (5) ◽

pp. 914-928 ◽

Cited By ~ 5

Author(s):

Christian Fensch ◽

Nick Barrow-Williams ◽

Robert D. Mullins ◽

Simon Moore

Keyword(s):

Chip Multiprocessors ◽

Physical Locality

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A study on optimally co-scheduling jobs of different lengths on chip multiprocessors

Proceedings of the 6th ACM conference on Computing frontiers - CF '09 ◽

10.1145/1531743.1531752 ◽

2009 ◽

Cited By ~ 23

Author(s):

Kai Tian ◽

Yunlian Jiang ◽

Xipeng Shen

Keyword(s):

Chip Multiprocessors ◽

On Chip

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Fast synchronization for chip multiprocessors

ACM SIGARCH Computer Architecture News ◽

10.1145/1105734.1105743 ◽

2005 ◽

Vol 33 (4) ◽

pp. 64-69 ◽

Cited By ~ 8

Author(s):

Jack Sampson ◽

Rubén González ◽

Jean-Francois Collard ◽

Norman P. Jouppi ◽

Mike Schlansker

Keyword(s):

Chip Multiprocessors

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Embedded RAIDs-on-chip for bus-based chip-multiprocessors

ACM Transactions on Embedded Computing Systems ◽

10.1145/2533316 ◽

2014 ◽

Vol 13 (4) ◽

pp. 1-36 ◽

Cited By ~ 2

Author(s):

Luis Angel D. Bathen ◽

Nikil D. Dutt

Keyword(s):

Chip Multiprocessors ◽

On Chip

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Improving the Restore Performance via Physical-Locality Middleware for Backup Systems

Proceedings of the 21st International Middleware Conference ◽

10.1145/3423211.3425691 ◽

2020 ◽

Author(s):

Pengfei Li ◽

Yu Hua ◽

Qin Cao ◽

Mingxuan Zhang

Keyword(s):

Physical Locality

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Task and Communication Allocation for Real-time Tasks to Networks-on-Chip Multiprocessors

2020 Second International Conference on Embedded & Distributed Systems (EDiS) ◽

10.1109/edis49545.2020.9296446 ◽

2020 ◽

Author(s):

Chawki Benchehida ◽

Mohammed Kamel Benhaoua ◽

Houssam-Eddine Zahaf ◽

Giuseppe Lipari

Keyword(s):

Real Time ◽

Chip Multiprocessors ◽

Networks On Chip ◽

On Chip

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Investigation of LSTM based prediction for dynamic energy management in chip multiprocessors

2017 Eighth International Green and Sustainable Computing Conference (IGSC) ◽

10.1109/igcc.2017.8323597 ◽

2017 ◽

Cited By ~ 2

Author(s):

Milad Ghorbani Moghaddam ◽

Wenkai Guan ◽

Cristinel Ababei

Keyword(s):

Energy Management ◽

Chip Multiprocessors ◽

Dynamic Energy Management

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NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351128 ◽

2018 ◽

Author(s):

Pooneh Safayenikoo ◽

Arghavan Asad ◽

Mahmood Fathy ◽

Farah Mohammadi

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Cache Architecture

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A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News ◽

10.1145/1024295.1024297 ◽

2004 ◽

Vol 32 (3) ◽

pp. 11-18 ◽

Cited By ~ 3

Author(s):

Partha Kundu ◽

Murali Annavaram ◽

Trung Diep ◽

John Shen

Keyword(s):

Chip Multiprocessors ◽

Instruction Cache ◽

On Chip

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Using data replication to reduce communication energy on chip multiprocessors

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05 ◽

10.1145/1120725.1121013 ◽

2005 ◽

Cited By ~ 5

Author(s):

M. Kandemir ◽

G. Chen ◽

F. Li ◽

I. Demirkiran

Keyword(s):

Chip Multiprocessors ◽

Data Replication ◽

Using Data ◽

On Chip

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Unified reliability estimation and management of NoC based chip multiprocessors

Microprocessors and Microsystems ◽

10.1016/j.micpro.2013.11.009 ◽

2014 ◽

Vol 38 (1) ◽

pp. 53-63 ◽

Cited By ~ 12

Author(s):

Alexandre Yasuo Yamamoto ◽

Cristinel Ababei

Keyword(s):

Chip Multiprocessors ◽

Reliability Estimation

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