Design of a Bufferless Photonic Clos Network-on-Chip Architecture

2014 ◽  
Vol 63 (3) ◽  
pp. 764-776 ◽  
Keyword(s):  
Network On Chip ◽  
Clos Network ◽  
On Chip

CNoC: High-Radix Clos Network-on-Chip

2011 ◽  
Vol 30 (12) ◽  
pp. 1897-1910 ◽  
Author(s):  
Yu-Hsiang Kao ◽  
Ming Yang ◽  
N. Sertac Artan ◽  
H. Jonathan Chao
Keyword(s):  
Network On Chip ◽  
Clos Network ◽  
High Radix ◽  
On Chip

Customizing Clos Network-on-Chip for Neural Networks

2017 ◽  
Vol 66 (11) ◽  
pp. 1865-1877 ◽  
Author(s):  
Reza Hojabr ◽  
Mehdi Modarressi ◽  
Masoud Daneshtalab ◽  
Ali Yasoubi ◽  
Ahmad Khonsari
Keyword(s):  
Neural Networks ◽  
Network On Chip ◽  
Clos Network ◽  
On Chip

Design of High-Radix Clos Network-on-Chip

2010 ◽  
Author(s):  
Yu-Hsiang Kao ◽  
Najla Alfaraj ◽  
Ming Yang ◽  
H. Jonathan Chao
Keyword(s):  
Network On Chip ◽  
Clos Network ◽  
High Radix ◽  
On Chip

scholarly journals Application of Butterfly Clos-Network in Network-on-Chip

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Hui Liu ◽  
Linquan Xie ◽  
Jiansheng Liu ◽  
Lei Ding
Keyword(s):  
Information Exchange ◽  
Complete Information ◽  
Network On Chip ◽  
Path Diversity ◽  
Traffic Pattern ◽  
Congested Traffic ◽  
Butterfly Network ◽  
Clos Network ◽  
The Rich ◽  
On Chip

This paper studied the topology of NoC (Network-on-Chip). By combining the characteristics of the Clos network and butterfly network, a new topology named BFC (Butterfly Clos-network) network was proposed. This topology integrates several modules, which belongs to the same layer but different dimensions, into a new module. In the BFC network, a bidirectional link is used to complete information exchange, instead of information exchange between different layers in the original network. During the routing period, other nondestination nodes can be used as middle stages to transfer data packets to complete the routing mission. Therefore, this topology has the characteristic of multistage. Simulation analyses show that BFC inherits the rich path diversity of Clos network, and it has a better performance than butterfly network in throughput and delay in a quite congested traffic pattern.

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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