Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation

2005 ◽  
Vol 54 (12) ◽  
pp. 1628-1630 ◽  
Author(s):  
Ku-Young Chang ◽  
Dowon Hong ◽  
Hyun-Sook Cho
Keyword(s):  
Low Complexity ◽  
Parallel Multiplier ◽  
Redundant Representation

scholarly journals New Concept of Universal Binary Multiplication and Its Implementation on FPGA

2021 ◽  
Vol 56 (3) ◽  
pp. 124-139
Author(s):  
Sarifuddin Madenda ◽  
Suryadi Harmanto ◽  
Astie Darmayantie
Keyword(s):  
Time Delay ◽  
Low Complexity ◽  
Negative Numbers ◽  
Parallel Multiplier ◽  
Software And Hardware

This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be a signed positive (SPN) or signed negative numbers (SNN). The universal multiplier can handle all (nine) types of multiplication, where each operand can be as unsigned(USN), signed positive, and signed negative numbers. For 8x8 bits, signed serial-parallel and signed parallel multipliers occupy19 LUTs and 58 LUTs with a logic time delay of 0.769 ns and 3.600 ns. Besides, for 8x8 bits, serial-parallel and parallel universal multipliers inhabit 21 LUTs and 60 LUTs with a logic time delay of 0.831ns and 3.677 ns, successively.

Low complexity bit-parallel multiplier forF2ndefined by repeated polynomials

2018 ◽  
Vol 241 ◽  
pp. 2-12
Author(s):  
Nam Su Chang ◽  
Eun Sook Kang ◽  
Seokhie Hong
Keyword(s):  
Low Complexity ◽  
Parallel Multiplier

A Low Complexity Splitter Based Parallel Multiplier for DSP Applications

2015 ◽  
Vol 85 (2) ◽  
pp. 277-281 ◽  
Author(s):  
Arvind Chakrapani ◽  
T. Elanchezian ◽  
G. Karthikeyan ◽  
N. Divya ◽  
K. Kabilarasan ◽  
...  
Keyword(s):  
Low Complexity ◽  
Parallel Multiplier ◽  
Dsp Applications

Low-Complexity Semi-Systolic Multiplier Using Redundant Representation Over Finite Fields

2017 ◽  
Vol 23 (10) ◽  
pp. 10325-10328
Author(s):  
Kee-Won Kim ◽  
Hyun-Ho Lee ◽  
Seung-Hoon Kim
Keyword(s):  
Finite Fields ◽  
Low Complexity ◽  
Redundant Representation ◽  
Systolic Multiplier

Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation

2006 ◽  
Vol 21 (6) ◽  
pp. 887-892 ◽  
Author(s):  
Chiou-Yng Lee ◽  
Jenn-Shyong Horng ◽  
I-Chang Jou
Keyword(s):  
Low Complexity ◽  
Dual Basis ◽  
Parallel Multiplier
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