Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions

P. Biswas; N.D. Dutt

doi:10.1109/tc.2005.157

Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions

IEEE Transactions on Computers ◽

10.1109/tc.2005.157 ◽

2005 ◽

Vol 54 (10) ◽

pp. 1216-1226 ◽

Cited By ~ 5

Author(s):

P. Biswas ◽

N.D. Dutt

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Code Size ◽

Instruction Set Extensions

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Instruction Set Encoding Optimization for Code Size Reduction

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation ◽

10.1109/icsamos.2007.4285728 ◽

2007 ◽

Cited By ~ 1

Author(s):

Michael Med ◽

Andreas Krall

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Code Size

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PARE: instruction set architecture for efficient code size reduction

Electronics Letters ◽

10.1049/el:19991420 ◽

1999 ◽

Vol 35 (24) ◽

pp. 2098 ◽

Cited By ~ 12

Author(s):

Young-Jun Kwon ◽

Xiarong Ma ◽

Hyuk Jae Lee

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Instruction Set Architecture ◽

Code Size ◽

Efficient Code

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Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions

Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03 ◽

10.1145/951710.951726 ◽

2003 ◽

Cited By ~ 3

Author(s):

Partha Biswas ◽

Nikil Dutt

Keyword(s):

Instruction Set ◽

Code Size ◽

Instruction Set Extensions

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CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

International Journal of Computing ◽

10.47839/ijc.3.2.279 ◽

2014 ◽

pp. 7-12

Author(s):

Xianhong Xu ◽

Simon Jones

Keyword(s):

Embedded Systems ◽

Size Reduction ◽

Software Implementation ◽

Instruction Set ◽

Code Size ◽

Code Compression ◽

Temporary Storage ◽

Level 2 ◽

Code Density ◽

Software Prototype

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

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