Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

P.P. Pande; C. Grecu; M. Jones; A. Ivanov; R. Saleh

doi:10.1109/tc.2005.134

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

IEEE Transactions on Computers ◽

10.1109/tc.2005.134 ◽

2005 ◽

Vol 54 (8) ◽

pp. 1025-1040 ◽

Cited By ~ 541

Author(s):

P.P. Pande ◽

C. Grecu ◽

M. Jones ◽

A. Ivanov ◽

R. Saleh

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Trade Offs ◽

Interconnect Architectures ◽

On Chip

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A Performance Evaluation for Optical Network-on-Chip Interconnect Architectures

Asia Communications and Photonics Conference and Exhibition ◽

10.1364/acp.2009.thd4 ◽

2009 ◽

Cited By ~ 1

Author(s):

Shiqing Wang ◽

Huaxi Gu

Keyword(s):

Performance Evaluation ◽

Optical Network ◽

Network On Chip ◽

Interconnect Architectures ◽

On Chip ◽

A Performance

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A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Microprocessors and Microsystems ◽

10.1016/j.micpro.2014.04.011 ◽

2014 ◽

Vol 38 (5) ◽

pp. 375-398 ◽

Cited By ~ 8

Author(s):

Sani Abba ◽

Jeong-A Lee

Keyword(s):

Performance Evaluation ◽

Networks On Chip ◽

Trade Offs ◽

Interconnect Architectures ◽

On Chip

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Design and Performance Evaluation of Hybrid Wired-Wireless Network on Chip Interconnect Architectures

Advances in Intelligent Systems and Computing - Third International Congress on Information and Communication Technology ◽

10.1007/978-981-13-1165-9_17 ◽

2018 ◽

pp. 191-199

Author(s):

Priyanka Mitra ◽

Bhavna Sharma ◽

Vinay Kumar Chandna ◽

Vijay Singh Rathore

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Interconnect Architectures ◽

And Performance ◽

On Chip

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Performance evaluation for optical network-on-chip interconnect architectures

10.1117/12.852107 ◽

2009 ◽

Author(s):

Shiqing Wang ◽

Huaxi Gu

Keyword(s):

Performance Evaluation ◽

Optical Network ◽

Network On Chip ◽

Interconnect Architectures ◽

On Chip

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Performance evaluation and design trade-offs for wireless network-on-chip architectures

ACM Journal on Emerging Technologies in Computing Systems ◽

10.1145/2287696.2287706 ◽

2012 ◽

Vol 8 (3) ◽

pp. 1-25 ◽

Cited By ~ 63

Author(s):

Kevin Chang ◽

Sujay Deb ◽

Amlan Ganguly ◽

Xinmin Yu ◽

Suman Prasad Sah ◽

...

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Trade Offs ◽

On Chip

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A Network on Chip Architecture and Performance Evaluation

2010 Second International Conference on Networks Security, Wireless Communications and Trusted Computing ◽

10.1109/nswctc.2010.91 ◽

2010 ◽

Cited By ~ 3

Author(s):

Wang Zhang ◽

Ligang Hou ◽

Lei Zuo ◽

Zhenyu Peng ◽

Wuchen Wu

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

And Performance ◽

On Chip

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Performance evaluation of cross link fully adaptive routing algorithm with cross link architecture for Network on Chip

2017 International Conference on Inventive Computing and Informatics (ICICI) ◽

10.1109/icici.2017.8365198 ◽

2017 ◽

Cited By ~ 2

Author(s):

Rohit Mahar ◽

Sudhanshu Choudhary

Keyword(s):

Performance Evaluation ◽

Routing Algorithm ◽

Adaptive Routing ◽

Network On Chip ◽

Cross Link ◽

Fully Adaptive ◽

On Chip

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Comparative performance evaluation of power and area Network on Chip (NoC) architectures

2012 IEEE International Conference on Computational Intelligence and Computing Research ◽

10.1109/iccic.2012.6510308 ◽

2012 ◽

Cited By ~ 2

Author(s):

A. Kalimuthu ◽

M. Karthikeyan

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Area Network ◽

Comparative Performance ◽

On Chip

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Design and performance evaluation of Mesh-of-Tree-based hierarchical wireless network-on-chip for multicore systems

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2018.09.008 ◽

2019 ◽

Vol 123 ◽

pp. 100-117 ◽

Cited By ~ 4

Author(s):

Abbas Dehghani ◽

Keyvan RahimiZadeh

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Multicore Systems ◽

And Performance ◽

On Chip

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Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

International Journal of Engineering ◽

10.5829/idosi.ije.2014.27.04a.01 ◽

2014 ◽

Vol 27 (4 (A)) ◽

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Research Note ◽

Routing Methods ◽

And Performance ◽

On Chip

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