Register Caching for Stencil Computations on GPUs

2014 ◽  
Author(s):  
Thomas L. Falch ◽  
Anne C. Elster
Keyword(s):  
Stencil Computations

scholarly journals Verified lifting of stencil computations

2016 ◽  
Vol 51 (6) ◽  
pp. 711-726 ◽  
Author(s):  
Shoaib Kamil ◽  
Alvin Cheung ◽  
Shachar Itzhaky ◽  
Armando Solar-Lezama
Keyword(s):  
Stencil Computations

scholarly journals Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors

SIAM Review ◽  
2009 ◽  
Vol 51 (1) ◽  
pp. 129-159 ◽  
Author(s):  
Kaushik Datta ◽  
Shoaib Kamil ◽  
Samuel Williams ◽  
Leonid Oliker ◽  
John Shalf ◽  
...  
Keyword(s):  
Performance Modeling ◽  
Stencil Computations ◽  
And Performance ◽  
Optimization And Performance

Noise-Tolerant Explicit Stencil Computations for Nonuniform Process Execution Rates

2015 ◽  
Vol 2 (1) ◽  
pp. 1-33 ◽  
Author(s):  
Adam Hammouda ◽  
Andrew R. Siegel ◽  
Stephen F. Siegel
Keyword(s):  
Stencil Computations ◽  
Process Execution ◽  
Execution Rates ◽  
Noise Tolerant

scholarly journals High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth Memory

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1275
Author(s):  
Changdao Du ◽  
Yoshiki Yamaguchi
Keyword(s):  
Programming Languages ◽  
High Performance ◽  
Design Space Exploration ◽  
Scale Up ◽  
High Level Synthesis ◽  
Stencil Computations ◽  
Temporal Domain ◽  
High Bandwidth ◽  
Promising Solution ◽  
High Level

Due to performance and energy requirements, FPGA-based accelerators have become a promising solution for high-performance computations. Meanwhile, with the help of high-level synthesis (HLS) compilers, FPGA can be programmed using common programming languages such as C, C++, or OpenCL, thereby improving design efficiency and portability. Stencil computations are significant kernels in various scientific applications. In this paper, we introduce an architecture design for implementing stencil kernels on state-of-the-art FPGA with high bandwidth memory (HBM). Traditional FPGAs are usually equipped with external memory, e.g., DDR3 or DDR4, which limits the design space exploration in the spatial domain of stencil kernels. Therefore, many previous studies mainly relied on exploiting parallelism in the temporal domain to eliminate the bandwidth limitations. In our approach, we scale-up the design performance by considering both the spatial and temporal parallelism of the stencil kernel equally. We also discuss the design portability among different HLS compilers. We use typical stencil kernels to evaluate our design on a Xilinx U280 FPGA board and compare the results with other existing studies. By adopting our method, developers can take broad parallelization strategies based on specific FPGA resources to improve performance.

A Multilevel Parallelization Framework for High-Order Stencil Computations

2009 ◽  
pp. 642-653 ◽  
Author(s):  
Hikmet Dursun ◽  
Ken-ichi Nomura ◽  
Liu Peng ◽  
Richard Seymour ◽  
Weiqiang Wang ◽  
...  
Keyword(s):  
High Order ◽  
Stencil Computations
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