Analysis of ultra-low voltage digital circuits over process variations

2012 ◽  
Author(s):  
Aaron Arthurs ◽  
Jia Di
Keyword(s):  
Digital Circuits ◽  
Low Voltage ◽  
Process Variations

scholarly journals Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 983 ◽  
Author(s):  
Pedro Toledo ◽  
Paolo Crovetti ◽  
Hamilton Klimach ◽  
Sergio Bampi
Keyword(s):  
Pulse Width Modulation ◽  
Low Voltage ◽  
Process Variations ◽  
Pulse Modulation ◽  
Silicon Area ◽  
Operational Transconductance Amplifiers ◽  
Static Calibration ◽  
Digital Pulse ◽  
Transconductance Amplifiers ◽  
The Impact

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

scholarly journals A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing

2021 ◽  
Vol 58 (1) ◽  
pp. 71-76
Author(s):  
Hassan Faraji Baghtash ◽  
Rasoul Pakdel
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Process Variations ◽  
High Gain ◽  
Biomedical Signal Processing ◽  
Noise Power ◽  
Well Performance ◽  
Subthreshold Region ◽  
Rail To Rail ◽  
Unity Gain

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.

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