Two stage CMOS operational transconductance amplifier for front-end electronics design using multiobjective genetic algorithms

Author(s):  
Abdelghani Dendouga ◽  
Slimane Oussalah
2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Abdelghani Dendouga ◽  
Slimane Oussalah ◽  
Damien Thienpont ◽  
Abdenour Lounis

The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) based circuit applications. Six performances are considered in this study, direct current (DC) gain, unity-gain bandwidth (GBW), phase margin (PM), power consumption (P), area (A), and slew rate (SR). We used the Matlab optimization toolbox to implement the program. Also, by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA) is simulated by using Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company) RF 0.18 μm CMOS technology. A good agreement is observed between the program optimization and electric simulation.


2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Tanya Vanessa Abaya ◽  
Frederick Ray I. Gomez

The paper presents a design of a two-stage fully-differential operational transconductance amplifier (OTA) for a 10-bit 40-Msamples/s Nyquist rate analog-to-digital converter (ADC) using  a standard 0.35µm complementary metal-oxide semiconductor (CMOS) process.  A telescopic cascode topology is implemented as main stage, with common source amplifiers as output stage for the differential outputs. The open loop amplifier achieved a gain of 108dB, while the closed loop gain is at 12dB with settling time of less than 11ns for an accuracy of 0.5%.  Total output noise achieved is 63.4uVrms.  Loop unity gain bandwidth is 205MHz with phase margin of 77.6°. The design has a dynamic range of 88.3dB, and power consumption of 26.6mW from a 3V supply.


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