High-Performance Architectures for Finite Field Inversion Over GF(2163)

In this paper, a new architecture for radix-2n serial–serial multiplication/reduction for the finite field GF(2m) is presented. The input operands are serially entered one digit at a time and the output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structure utilizes a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structure possesses features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. Also, a systolic scalable area efficient design which provides a 50% reduction in hardware without degrading the speed performance is proposed. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.

Download Full-text

HIGH PERFORMANCE SCALABLE MIXED-RADIX-2n SERIAL-SERIAL MULTIPLIERS FOR GF(2m)

Journal of Circuits System and Computers ◽

10.1142/s0218126610006621 ◽

2010 ◽

Vol 19 (05) ◽

pp. 1089-1107 ◽

Cited By ~ 1

Author(s):

ABDURAZZAG SULAIMAN ALMILADI

Keyword(s):

Finite Field ◽

High Performance ◽

Design Requirement ◽

Efficient Utilization ◽

Serial Transfer ◽

Transfer Data ◽

Time Performance

In this paper, two new high performance bidirectional mixed radix-2n serial-serial multipliers for the finite field GF (2m) are presented. The input operands are serially entered one digit at a time for the first operand and two digits at a time for the second operand. The output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure in the same manner so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structures utilize a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structures possess features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. The new twin pipe design has improved the area-time performance by ~37% when compared with the best existing radix-2n serial-serial multipliers for the finite field GF (2m) . Furthermore, it is the first twin pipe bidirectional radix-2n serial-serial multiplier for the finite field GF (2m) reported in the literature. The twin pipe multiplier can be used to perform two successive K-digit multiplications in 2K + 6 cycles without truncating the results. As a consequence, a new data can be fed into the multiplier every K + 3 cycles. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.

Download Full-text

High-speed systolic architectures for finite field inversion and division

Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04 ◽

10.1145/988952.989064 ◽

2004 ◽

Cited By ~ 2

Author(s):

Zhiyuan Yan ◽

Dilip V. Sarwate

Keyword(s):

Finite Field ◽

High Speed ◽

Field Inversion

Download Full-text

High-performance field inversion capillary electrophoresis of 0.1-23 kbp DNA fragments with low-gelling, replaceable agarose gels

Electrophoresis ◽

10.1002/elps.1150170908 ◽

1996 ◽

Vol 17 (9) ◽

pp. 1443-1450 ◽

Cited By ~ 11

Author(s):

Nong Chen ◽

Lijuan Wu ◽

Anders Palm ◽

Tasanee Srichaiyo ◽

Stellan Hjertén

Keyword(s):

Capillary Electrophoresis ◽

High Performance ◽

Dna Fragments ◽

Agarose Gels ◽

Field Inversion

Download Full-text