A high gain down-conversion mixer in 0.18um CMOS technology for ultra wideband applications

2016 ◽  
Author(s):  
Uttam Kumar Sharma ◽  
Abhay Chaturvedi ◽  
Manish Kumar
Keyword(s):  
Cmos Technology ◽  
High Gain ◽  
Ultra Wideband ◽  
Down Conversion

A K-Band High-Gain Down-Conversion Mixer in 0.18 $\mu$m CMOS Technology

2009 ◽  
Vol 19 (4) ◽  
pp. 227-229 ◽  
Author(s):  
Dukju Ahn ◽  
Dong-Wook Kim ◽  
Songcheol Hong
Keyword(s):  
Cmos Technology ◽  
High Gain ◽  
Down Conversion ◽  
K Band

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

High Gain Printed Ultra Wideband Antenna Concept

2007 ◽  
Author(s):  
Veselin Brankovic ◽  
Adalbert Jordan ◽  
Djordje Simic ◽  
Jens Weber ◽  
Jagjit Bal
Keyword(s):  
High Gain ◽  
Ultra Wideband ◽  
Wideband Antenna

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

A window detection technique with adjustable threshold for transmitted reference receivers

2013 ◽  
Vol 3 (1) ◽  
Author(s):  
Apratim Roy ◽  
A. Rashid
Keyword(s):  
Input Data ◽  
Cmos Technology ◽  
Ultra Wideband ◽  
Power Requirement ◽  
The Core ◽  
Transmitted Reference ◽  
Detection Circuit ◽  
Detection Window ◽  
Improved Performance ◽  
Decision Circuit

AbstractThis paper presents a threshold decision circuit with an adjustable detection window designed in a 90-nm IBM CMOS technology. Together with an RF mixer, the decision Section realizes the circuit implementation of the back-end of a transmitted reference ultra wideband receiver, which is yet to be reported in literature. The proposed circuit is built on a differential amplifier core and avoids the use of integrator and sampling blocks, which reduces the device burden necessary for the architecture. Moreover, the detection window threshold of the design can be regulated by three independent factors defined by the circuit elements. The circuit is tested at an input data rate of 0.1∼2.0 Gbps and the core decision section consumes 9.14 mW from a 1.2-V bias supply (with a maximum capacity/Pdc ratio of 218.8 GHz/W). When compared against other reported decision blocks, the proposed detection circuit shows improved performance in terms of capacity and power requirement.

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