Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC

2008 ◽  
Author(s):  
Dongyeob Chun ◽  
Joonho Kim ◽  
Seonyoung Lee ◽  
Kyeongsoon Cho
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Video Codec

An Improved Object-Based Video Segmentation Method

2012 ◽  
Vol 220-223 ◽  
pp. 2445-2449
Author(s):  
Wen Dan Xu ◽  
Xin Quan Lai ◽  
Dong Lai Xu
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Video Segmentation ◽  
Error Function ◽  
Least Square ◽  
Video Frame ◽  
Merging Process ◽  
Initial Segmentation ◽  
Two Stages

This paper presents an improved video segmentation scheme, which consists of two stages: initial segmentation and motion estimation. In the initial segmentation, the watershed transformation followed by a region adjacency graph guided region merging process is used to partition the first video frame into spatial homogenous regions. Then the motion of changed region is estimated. Based on the highly efficient quadratic motion model, the motion estimation is undertaken using Gauss-Newton Levenberg-Marquardt method to minimize the least-square error function. Experimental results show the proposed scheme provides high performance in terms of segmentation accuracy and video compression ratio.

A high performance hardware architecture for multi-frame hierarchical motion estimation

2011 ◽  
Vol 57 (2) ◽  
pp. 794-801 ◽  
Author(s):  
Huong Ho ◽  
Robert Klepko ◽  
Nam Ninh ◽  
Demin Wang
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Hardware Architecture

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

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