Effects of Interconnect Process Variations on Signal Integrity

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the â€œspeedsâ€ on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book â€œ2-D Electromagnetic Simulation of Passive Microstrip Circuitsâ€ from the corresponding author of this paper.

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Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0539 ◽

2002 ◽

Author(s):

Yoav Weizman ◽

Ezra Baruch ◽

Michael Zimin

Keyword(s):

Failure Analysis ◽

Process Variations ◽

Fault Isolation ◽

Operating Conditions ◽

Detection Sensitivity ◽

Isolation Technique ◽

Root Cause ◽

Emission Microscopy ◽

Failure Location ◽

Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

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