VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera

2006 IEEE International SOC Conference ◽

10.1109/socc.2006.283868 ◽

2006 ◽

Cited By ~ 6

Author(s):

O. Adamo ◽

Saraju Mohanty ◽

E. Kougianos ◽

M. Varanasi

Keyword(s):

Vlsi Architecture

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A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e99.a.2375 ◽

2016 ◽

Vol E99.A (12) ◽

pp. 2375-2387

Author(s):

Heming SUN ◽

Dajiang ZHOU ◽

Shuping ZHANG ◽

Shinji KIMURA

Keyword(s):

Low Power ◽

Vlsi Architecture ◽

Inverse Transform

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A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

IEICE Electronics Express ◽

10.1587/elex.10.20130210 ◽

2013 ◽

Vol 10 (9) ◽

pp. 20130210-20130210 ◽

Cited By ~ 2

Author(s):

Hong Liang ◽

He Weifeng ◽

Zhu Hui ◽

Mao Zhigang

Keyword(s):

Block Size ◽

Vlsi Architecture

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Novel Bit-Sliced Near-Memory Computing Based VLSI Architecture for Fast Sobel Edge Detection in IoT Edge Devices

2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) ◽

10.1109/ises50453.2020.00071 ◽

2020 ◽

Author(s):

Rajeev Joshi ◽

Md Adnan Zaman ◽

Srinivas Katkoori

Keyword(s):

Edge Detection ◽

Vlsi Architecture ◽

Sobel Edge Detection

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A Novel VLSI Architecture for Barrel Distortion Correction

2020 International Computer Symposium (ICS) ◽

10.1109/ics51289.2020.00050 ◽

2020 ◽

Author(s):

Chi-Ting Ni ◽

Chen-An Chang ◽

Jia-Wei Liao ◽

Pei-Yin Chen

Keyword(s):

Vlsi Architecture ◽

Distortion Correction ◽

Barrel Distortion

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Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2020.3038417 ◽

2020 ◽

pp. 1-13

Author(s):

Fei Lyu ◽

Xiaoqi Xu ◽

Yu Wang ◽

Yuanyong Luo ◽

Yuxuan Wang ◽

...

Keyword(s):

Linear Approximation ◽

Approximation Method ◽

Vlsi Architecture ◽

Floating Point ◽

Linear Approximation Method ◽

Floating Point Numbers

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An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) ◽

10.1109/icecs49266.2020.9294943 ◽

2020 ◽

Author(s):

Patricia U. L. da Costa ◽

Guilherme Paim ◽

Leandro Rocha ◽

Eduardo da Costa ◽

Sergio Almeida ◽

...

Keyword(s):

Vlsi Architecture

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VLSI Architecture of Flexible Macroblock Ordering Manchester Encoding with Sols Method

Journal of Physics Conference Series ◽

10.1088/1742-6596/1964/6/062093 ◽

2021 ◽

Vol 1964 (6) ◽

pp. 062093

Author(s):

L Srinivas ◽

G Upender ◽

N L Aravinda

Keyword(s):

Vlsi Architecture ◽

Flexible Macroblock Ordering

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An Efficient High-Speed Lifting Based 1D/2D-DWT VLSI Architecture Using CDF-5/3 Wavelet Transform For Image Processing Applications

2020 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) ◽

10.1109/rteict49044.2020.9315649 ◽

2020 ◽

Author(s):

M Sushmitha ◽

S Chetan ◽

Sayantam Sarkar

Keyword(s):

Image Processing ◽

Wavelet Transform ◽

High Speed ◽

Vlsi Architecture

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Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2020.2992514 ◽

2020 ◽

Vol 67 (12) ◽

pp. 3532-3536

Author(s):

Suresh Mopuri ◽

Amit Acharyya

Keyword(s):

Design Methodology ◽

Vlsi Architecture ◽

Low Complexity ◽

Architecture Design

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Highly pipelined VLSI architecture for computation of fast Fourier transforms

10.1117/12.160427 ◽

1993 ◽

Cited By ~ 4

Author(s):

Hong-Jin Yeh

Keyword(s):

Fourier Transforms ◽

Vlsi Architecture ◽

Fast Fourier Transforms

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