A circuit-switched network architecture for network-on-chip

2004 ◽  
Author(s):  
Ran Liu ◽  
L.-R. Zheng ◽  
H. Tenhunen
Keyword(s):  
Network Architecture ◽  
Network On Chip ◽  
Switched Network ◽  
On Chip

High performance hybrid-switched network-on-chip using shortcut paths

2016 ◽  
Author(s):  
Sina Sayardoost Tabrizi ◽  
Iman Soltani Mohammadi ◽  
Abbas Mazloumi ◽  
Mehdi Modarressi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Switched Network ◽  
On Chip

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS

2008 ◽  
Author(s):  
Mark Anders ◽  
Himanshu Kaul ◽  
Martin Hansson ◽  
Ram Krishnamurthy ◽  
Shekhar Borkar
Keyword(s):  
Network On Chip ◽  
Switched Network ◽  
On Chip

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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