System interconnect design exploration for embedded MPSoCs

2011 ◽  
Author(s):  
Chen-Ling Chou ◽  
Radu Marculescu ◽  
Umit Ogras ◽  
Satrajit Chatterjee ◽  
Michael Kishinevsky ◽  
...  
Keyword(s):  
Design Exploration ◽  
Interconnect Design

Neural-based Transient Behavioral Modeling of IC Buffers for High-speed Interconnect Design

PIERS Online ◽  
2007 ◽  
Vol 3 (7) ◽  
pp. 1136-1138
Author(s):  
Yi Cao ◽  
Qijun Zhang ◽  
Ihsan Erdin
Keyword(s):  
High Speed ◽  
Behavioral Modeling ◽  
Interconnect Design

A Design Exploration Framework for Secure IoT-Systems

2020 ◽  
Author(s):  
Lukas Gressl ◽  
Alexander Rech ◽  
Christian Steger ◽  
Andreas Sinnhofer ◽  
Ralph Weissnegger
Keyword(s):  
Design Exploration

scholarly journals OutlierNets: Highly Compact Deep Autoencoder Network Architectures for On-Device Acoustic Anomaly Detection

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4805
Author(s):  
Saad Abbasi ◽  
Mahmoud Famouri ◽  
Mohammad Javad Shafiee ◽  
Alexander Wong
Keyword(s):  
Machine Learning ◽  
Anomaly Detection ◽  
Detection Methods ◽  
Detection Accuracy ◽  
Network Architectures ◽  
Design Exploration ◽  
Convolutional Autoencoder ◽  
Acoustic Anomaly ◽  
Human Operators ◽  
Computational Resources

Human operators often diagnose industrial machinery via anomalous sounds. Given the new advances in the field of machine learning, automated acoustic anomaly detection can lead to reliable maintenance of machinery. However, deep learning-driven anomaly detection methods often require an extensive amount of computational resources prohibiting their deployment in factories. Here we explore a machine-driven design exploration strategy to create OutlierNets, a family of highly compact deep convolutional autoencoder network architectures featuring as few as 686 parameters, model sizes as small as 2.7 KB, and as low as 2.8 million FLOPs, with a detection accuracy matching or exceeding published architectures with as many as 4 million parameters. The architectures are deployed on an Intel Core i5 as well as a ARM Cortex A72 to assess performance on hardware that is likely to be used in industry. Experimental results on the model’s latency show that the OutlierNet architectures can achieve as much as 30x lower latency than published networks.

scholarly journals A RF Redundant TSV Interconnection for High Resistance Si Interposer

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 169
Author(s):  
Mengcheng Wang ◽  
Shenglin Ma ◽  
Yufeng Jin ◽  
Wei Wang ◽  
Jing Chen ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
High Frequency ◽  
High Performance ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Equivalent Circuit Model ◽  
High Resistivity ◽  
Performance Requirements ◽  
Wave Radar ◽  
Interconnect Design

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

scholarly journals Interactive Exploration of Large-Scale UI Datasets with Design Maps

2021 ◽  
Author(s):  
Luis A Leiva ◽  
Asutosh Hota ◽  
Antti Oulasvirta
Keyword(s):  
User Interface ◽  
Point Cloud ◽  
Large Scale ◽  
Mobile Apps ◽  
Online Resources ◽  
Design Tools ◽  
Support Design ◽  
Design Exploration ◽  
Clustering Techniques ◽  
Cloud Points

Abstract Designers are increasingly using online resources for inspiration. How to best support design exploration without compromising creativity? We introduce and study Design Maps, a class of point-cloud visualizations that makes large user interface datasets explorable. Design Maps are computed using dimensionality reduction and clustering techniques, which we analyze thoroughly in this paper. We present concepts for integrating Design Maps into design tools, including interactive visualization, local neighborhood exploration and functionality to integrate existing solutions to the design at hand. These concepts were implemented in a wireframing tool for mobile apps, which was evaluated with actual designers performing realistic tasks. Overall, designers find Design Maps supporting their creativity (avg. CSI score of 74/100) and indicate that the maps producing consistent whitespacing within cloud points are the most informative ones.

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