A high-throughput multi-rate LDPC decoder for error correction of solid-state drives

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

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A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International ◽

10.1109/3dic.2012.6263023 ◽

2012 ◽

Cited By ~ 1

Author(s):

Teruyoshi Hatanaka ◽

Koh Johguchi ◽

Ken Takeuchi

Keyword(s):

Solid State ◽

Output Voltage ◽

Integration Method ◽

Boost Converter ◽

Solid State Drives ◽

3D Integration ◽

Voltage Degradation

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A novel error correction protocol for continuous variable quantum key distribution

Scientific Reports ◽

10.1038/s41598-021-90055-3 ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Kadir Gümüş ◽

Tobias A. Eriksson ◽

Masahiro Takeoka ◽

Mikio Fujiwara ◽

Masahide Sasaki ◽

...

Keyword(s):

Error Correction ◽

Quantum Key Distribution ◽

Ldpc Codes ◽

Key Distribution ◽

Continuous Variable ◽

Early Termination ◽

Parity Check ◽

Secret Key ◽

Ldpc Decoder ◽

And Performance

AbstractReconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

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