K-nested layered look-ahead method and architectures for high throughput Viterbi decoder

2004 ◽  
Author(s):  
Jun Jin Kong ◽  
K.K. Parhi
Keyword(s):  
High Throughput ◽  
Viterbi Decoder ◽  
Look Ahead

A High-throughput Parallel Viterbi Algorithm via Bitslicing

2021 ◽  
Vol 8 (4) ◽  
pp. 1-25
Author(s):  
Saleh Khalaj Monfared ◽  
Omid Hajihassani ◽  
Vahid Mohsseni ◽  
Dara Rahmati ◽  
Saeid Gorgin
Keyword(s):  
High Throughput ◽  
High Performance ◽  
Viterbi Algorithm ◽  
Data Representation ◽  
Processing Unit ◽  
Viterbi Decoder ◽  
Soft Decision ◽  
Content Type ◽  
Data Intensive ◽  
Representation Scheme

In this work, we present a novel bitsliced high-performance Viterbi algorithm suitable for high-throughput and data-intensive communication. A new column-major data representation scheme coupled with the bitsliced architecture is employed in our proposed Viterbi decoder that enables the maximum utilization of the parallel processing units in modern parallel accelerators. With the help of the proposed alteration of the data scheme, instead of the conventional bit-by-bit operations, 32-bit chunks of data are processed by each processing unit. This means that a single bitsliced parallel Viterbi decoder is capable of decoding 32 different chunks of data simultaneously. Here, the Viterbi’s Add-Compare-Select procedure is implemented with our proposed bitslicing technique, where it is shown that the bitsliced operations for the Viterbi internal functionalities are efficient in terms of their performance and complexity. We have achieved this level of high parallelism while keeping an acceptable bit error rate performance for our proposed methodology. Our suggested hard and soft-decision Viterbi decoder implementations on GPU platforms outperform the fastest previously proposed works by 4.3{\times } and 2.3{\times } , achieving 21.41 and 8.24 Gbps on Tesla V100, respectively.

scholarly journals DESIGN OF HIGH THROUGHPUT ADD COMPARE AND SELECT UNIT FOR LOW POWER VITERBI DECODER

2021 ◽  
Vol 9 (1) ◽  
pp. 954-960
Author(s):  
Sudhakar Jyothula, Vijaya Sree Ganta , Ramesh Babu Chukka
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Data Communication ◽  
Junction Temperature ◽  
State Transitions ◽  
Low Latency ◽  
Viterbi Decoder ◽  
Output State ◽  
Trace Back ◽  
Ripple Carry Adder

The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and selects the lower metric value as a survivor path. SMU stores the data bits which utilizes the trace back method to fetch the likelihood path from the current state to a previous state. An ACS unit is an essential block for VD. The basic recursive ACSU design consists of Ripple Carry Adder (RCA), Comparator and a Selector block, which consume more area, power and operates with high junction temperature. To overcome these drawbacks, a modified ACSU design is implemented with recursive cancellation technique. ACS unit is modified by including a trace back mechanism to obtain a low latency and high speed in VD. It is designed with low complexity multiplexers, adders, logical AND gate and comparator block. This breaking recursive ACSU design utilizes less power, high throughput, low latency and also operates at low temperature. This analysis and simulation process are accomplished using Vivado Design Suite.

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