Design of DSP instructions and their hardware architecture for a Reed-Solomon codec

2003 ◽  
Author(s):  
J.S. Lee ◽  
M.H. Sunwoo ◽  
S.K. Oh
Keyword(s):  
Hardware Architecture

A New Hardware Architecture for Fuzzy Logic System Acceleration

2016 ◽  
Vol 12 (2) ◽  
pp. 188-197
Author(s):  
A yahoo.com ◽  
Aumalhuda Gani Abood aumalhuda ◽  
A comp ◽  
Dr. Mohammed A. Jodha ◽  
Dr. Majid A. Alwan
Keyword(s):  
Fuzzy Logic ◽  
Fuzzy Logic System ◽  
Hardware Architecture ◽  
Logic System

4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding

2020 ◽  
Author(s):  
Matheus Jahnke ◽  
Jones Goebel ◽  
Daniel Palomino ◽  
Guilherme Correa ◽  
Luciano Agostini ◽  
...  
Keyword(s):  
Light Field ◽  
Hardware Architecture

scholarly journals Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

2021 ◽  
Author(s):  
Parastoo Soleimani ◽  
David W. Capson ◽  
Kin Fun Li
Keyword(s):  
Real Time ◽  
Memory Management ◽  
Scale Space ◽  
Image Resolution ◽  
Hardware Architecture ◽  
Frame Rate ◽  
Time Sharing ◽  
Scale Invariant ◽  
Nonlinear Scale Space ◽  
Nonlinear Scale

AbstractThe first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a $$1280 \times 768$$ 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work.

A New PRNG Hardware Architecture Based on an Exponential Chaotic Map

2021 ◽  
Author(s):  
Matheus B. R. Cardoso ◽  
Samuel S. da Silva ◽  
Lucas G. Nardo ◽  
Roberto M. Passos ◽  
Erivelton G. Nepomuceno ◽  
...  
Keyword(s):  
Chaotic Map ◽  
Hardware Architecture
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