FPGA implementation of high speed multiplierless frequency response masking FIR filters

2002 ◽  
Author(s):  
Yong Lian
Keyword(s):  
Frequency Response ◽  
High Speed ◽  
Fpga Implementation ◽  
Fir Filters ◽  
Frequency Response Masking

A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS

2003 ◽  
Vol 12 (05) ◽  
pp. 643-654 ◽  
Author(s):  
YONG LIAN
Keyword(s):  
Frequency Response ◽  
High Speed ◽  
Sampling Frequency ◽  
Fir Filters ◽  
Throughput Rate ◽  
Shaping Filter ◽  
Filter Structure ◽  
Frequency Response Masking ◽  
Digital Fir Filters ◽  
Frm Approach

This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

An improved frequency response masking approach for designing sharp FIR filters

2001 ◽  
Vol 81 (12) ◽  
pp. 2573-2581 ◽  
Author(s):  
Yong Lian ◽  
Lei Zhang ◽  
Chi Chung Ko
Keyword(s):  
Frequency Response ◽  
Fir Filters ◽  
Frequency Response Masking
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