A simulation tool for design error models utilizing error compression and sampling

Optimized and efficient decision-making systems is the burning topic of research in modern manufacturing industry. The aforesaid statement is validated by the fact that the limitations of traditional decision-making system compresses the length and breadth of multi-objective decision-system application in FMS. The bright area of FMS with more complexity in control and reduced simpler configuration plays a vital role in decision-making domain. The decision-making process consists of various activities such as collection of data from shop floor; appealing the decision-making activity; evaluation of alternatives and finally execution of best decisions. While studying and identifying a suitable decision-making approach the key critical factors such as decision automation levels, routing flexibility levels and control strategies are also considered. This paper investigates the cordial relation between the system ideality and process response time with various prospective of decision-making approaches responsible for shop-floor control of FMS. These cases are implemented to a real-time FMS problem and it is solved using ARENA simulation tool. ARENA is a simulation software that is used to calculate the industrial problems by creating a virtual shop floor environment. This proposed topology is being validated in real time solution of FMS problems with and without implementation of decision system in ARENA simulation tool. The real-time FMS problem is considered under the case of full routing flexibility. Finally, the comparative analysis of the results is done graphically and conclusion is drawn.

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Simulation Tool for Assignment Models: SIMASI

INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY ◽

10.24297/ijct.v13i8.7070 ◽

2014 ◽

Vol 13 (8) ◽

pp. 4723-4728

Author(s):

Pratiksha Saxena ◽

Smt. Anjali

Keyword(s):

Optimization Procedure ◽

Simulation Tool ◽

Optimization Strategy ◽

Performance Measurements ◽

Integrated Simulation ◽

Assignment Model ◽

Classical Models ◽

Simulation Results ◽

User Friendly ◽

Assignment Models

In this paper, an integrated simulation optimization model for the assignment problems is developed. An effective algorithm is developed to evaluate and analyze the back-end stored simulation results. This paper proposes simulation tool SIMASI (Simulation of assignment models) to simulate assignment models. SIMASI is a tool which simulates and computes the results of different assignment models. This tool is programmed in DOT.NET and is based on analytical approach to guide optimization strategy. Objective of this paper is to provide a user friendly simulation tool which gives optimized assignment model results. Simulation is carried out by providing the required values of matrix for resource and destination requirements and result is stored in the database for further comparison and study. Result is obtained in terms of the performance measurements of classical models of assignment system. This simulation tool is interfaced with an optimization procedure based on classical models of assignment system. The simulation results are obtained and analyzed rigorously with the help of numerical examples.

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Identification in Dynamic Shock-Error Models

10.1007/978-3-642-95339-2 ◽

1979 ◽

Cited By ~ 31

Author(s):

Agustin Maravall ◽

Klaus Neumann ◽

Ulrich Steinhardt

Keyword(s):

Error Models

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Robust estimation in measurement error models

10.31274/rtd-180813-11622 ◽

1992 ◽

Author(s):

Joseph H.R Croos

Keyword(s):

Measurement Error ◽

Robust Estimation ◽

Error Models ◽

Measurement Error Models

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Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0103 ◽

2011 ◽

Author(s):

Yu Huang ◽

Wu-Tung Cheng ◽

Ting-Pu Tai ◽

Liyang Lai ◽

Ruifeng Guo ◽

...

Keyword(s):

Hold Time ◽

Clock Signal ◽

Clock Tree ◽

Scan Testing ◽

Design Error ◽

Functional Logic ◽

Scan Chains ◽

Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

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