Majority carrier accumulation in low-temperature-grown GaAs layer inserted into n-and p-type matrices

Author(s):  
P.N. Brunkov ◽  
V.V. Chaldyshev ◽  
A.V. Chernigovskii ◽  
A.A. Suvorova ◽  
N.A. Bert ◽  
...  
2000 ◽  
Vol 623 ◽  
Author(s):  
J. C. Ferrer ◽  
Z. Liliental-Weber ◽  
H. Reese ◽  
Y.J. Chiu ◽  
E. Hu

AbstractThe lateral thermal oxidation process of Al0.98Ga0.02As layers has been studied by transmission electron microscopy. Growing a low-temperature GaAs layer below the Al0.98Ga0.02As has been shown to result in better quality of the oxide/GaAs interfaces compared to reference samples. While the later have As precipitation above and below the oxide layer and roughness and voids at the oxide/GaAs interface, the structures with low-temperature have less As precipitation and develop interfaces without voids. These results are explained in terms of the diffusion of the As toward the low temperature layer. The effect of the addition of a Si02 cap layer is also discussed.


2016 ◽  
Vol 50 (11) ◽  
pp. 1499-1505 ◽  
Author(s):  
A. N. Kosarev ◽  
V. V. Chaldyshev ◽  
V. V. Preobrazhenskii ◽  
M. A. Putyato ◽  
B. R. Semyagin

1995 ◽  
Author(s):  
T. M. Cheng ◽  
C. Y. Chang ◽  
G. R. Lin ◽  
F. Ganikhanov ◽  
C. L. Pan ◽  
...  

1996 ◽  
Vol 448 ◽  
Author(s):  
D.B. Janes ◽  
S. Hong ◽  
V. R. Kolagunta ◽  
D. McInturff ◽  
T.-B. NG ◽  
...  

AbstractThe chemical stability of a GaAs layer structure consisting of a thin (10 nm) layer of low-temperature-grown GaAs (LTG:GaAs) on a heavily n-doped GaAs layer, both grown by molecular beam epitaxy, is described. Scanning tunneling spectroscopy and X-ray photoelectron spectroscopy performed after atmospheric exposure indicate that the LTG:GaAs surface layer oxidizes much less rapidly than comparable layers of stoichiometric GaAs. There is also evidence that the terminal oxide thickness is smaller than that of stoichiometric GaAs. The spectroscopy results are used to confirm a model for conduction in low resistance, nonalloyed contacts employing comparable layer structures. The inhibited surface oxidation rate is attributed to the bulk Fermi level pinning and the low minority carrier lifetime in unannealed LTG:GaAs. Device applications including low-resistance cap layers for field-effect transistors are described.


2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


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