A dynamic range differential capacitive sensor interface circuit with noise shaping model of sigma-delta modulator

2016 ◽  
Author(s):  
Sourav Bhattacharyya ◽  
Karunamoy Chatterjee ◽  
Sankar Narayan Mahato
Keyword(s):  
Dynamic Range ◽  
Capacitive Sensor ◽  
Noise Shaping ◽  
Sensor Interface ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Interface Circuit

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A 99.7-dB DR fourth-order sigma–delta modulator for digital gyroscope sensor

2017 ◽  
Vol 31 (09) ◽  
pp. 1750097 ◽  
Author(s):  
Xin-Peng Di ◽  
Wei-Ping Chen ◽  
Liang Yin ◽  
Xiao-Wei Liu
Keyword(s):  
Fourth Order ◽  
Dynamic Range ◽  
Low Frequency ◽  
Effective Area ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Transconductance Amplifier ◽  
Sample Frequency ◽  
Gyroscope Sensor

A fourth-order single-loop 1-bit sigma–delta [Formula: see text] modulator for digital gyroscope sensor interface circuit is presented in this paper. The effects caused by mismatch between parasite capacitors at the input of the operational transconductance amplifier (OTA) and the nonlinear on-resistance of the CMOS switch are analyzed. The chopping technique is adopted to eliminate the flick noise in low frequency. The modulator is fabricated in a standard CMOS 0.5-[Formula: see text] process and the effective area is 2 mm2. The power dissipation is 9.66 mW when the voltage is 5 V. The tested results show that a 93.7-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 99.7-dB dynamic range (DR) are achievable at the sample frequency of 500 kHz for 2 kHz bandwidth. The optimization of the switches used in the first integrator and the parasite capacity is proved to be effective in the design of modulator.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

2002 ◽  
Vol 37 (1) ◽  
pp. 2-10 ◽  
Author(s):  
O. Oliaei ◽  
P. Clement ◽  
P. Gorisse
Keyword(s):  
Dynamic Range ◽  
Sigma Delta Modulator ◽  
Sigma Delta
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