Efficient 16-bit Floating-Point Interval Processor for Embedded Systems and Applications

2006 ◽  
Author(s):  
Stephane Piskorski ◽  
Lionel Lacassagne
Keyword(s):  
Embedded Systems ◽  
Floating Point

Floating-point accelerator for biometric recognition on FPGA embedded systems

2018 ◽  
Vol 112 ◽  
pp. 20-34 ◽  
Author(s):  
E. Cantó-Navarro ◽  
M. López-García ◽  
R. Ramos-Lara
Keyword(s):  
Embedded Systems ◽  
Floating Point ◽  
Biometric Recognition

scholarly journals SoC opportunities for boosting SDR GNSS performance

2019 ◽  
pp. 457-462
Author(s):  
A A Kumarin ◽  
I A Kudryavtsev
Keyword(s):  
Signal Processing ◽  
Computational Complexity ◽  
Embedded Systems ◽  
Software Defined Radio ◽  
System On Chip ◽  
Floating Point ◽  
Computational Performance ◽  
Gnss Receivers ◽  
On Chip ◽  
High Flexibility

Software-defined-radio (SDR) becomes an attractive technique for the development of GNSS receivers due to universal hardware and high flexibility. However, the performance of signal processing can be a challenging task. Real-time mode implementation requires fast floating point calculations in several threads, not available for most part of embedded systems. This paper describes the system-on-chip based device drastically increasing computational performance. A summary of computational complexity of each stage of GNSS receiver is provided and several particular solutions are proposed.

scholarly journals Salsa: An Automatic Tool to Improve the Numerical Accuracy of Programs

10.29007/j2fd ◽  
2018 ◽  
Author(s):  
Nasrine Damouche ◽  
Matthieu Martel
Keyword(s):  
Numerical Analysis ◽  
Embedded Systems ◽  
Software Architecture ◽  
Static Analysis ◽  
Abstract Interpretation ◽  
Experimental Results ◽  
Floating Point ◽  
Numerical Accuracy ◽  
Automatic Tool ◽  
Concise Description

This article describes Salsa, an automatic tool to improve the accuracy of the floating- point computations done in numerical codes. Based on static analysis methods by abstract interpretation, our tool takes as input an original program, applies to it a set of transformations and then generates an optimized program which is more accurate than the initial one. The original and the transformed programs are written in the same imperative language. This article is a concise description of former work on the techniques implemented in Salsa, extended with a presentation of the main software architecture, the inputs and outputs of the tool as well as experimental results obtained by applying our tool on a set of sample programs coming from embedded systems and numerical analysis.

scholarly journals A NOVEL QUOTIENT PREDICTION FOR FLOATING-POINT DIVISION

2020 ◽  
Vol 38 (02) ◽  
Author(s):  
PHAM TRAN BICH THUAN
Keyword(s):  
Optimal Control ◽  
Signal Processing ◽  
Control System ◽  
Embedded Systems ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Floating Point ◽  
Prediction Algorithm ◽  
Look Up Table ◽  
Number Of Iterations

At present, floating-point operations are used as add-on functions in critical embedded systems, such as physics, aerospace system, nuclear simulation, image and digital signal processing, automatic control system and optimal control and financial, etc. However, floating-point division is slower than floating-point multiplication. To solve this problem, many existing works try to reduce the required number of iterations, which exploit large Look Up Table (LUT) resource to achieve approximate mantissa of a quotient. In this paper, we propose a novel prediction algorithm to achieve an optimal quotient by predicting certain bits in a dividend and a divisor, which reduces the required LUT resource. Therefore, the final quotient is achieved by accumulating all predicted quotients using our proposed prediction algorithm. The experimental results show that only 3 to 5 iterations are required to obtain the final quotient in a floating-point division computation. In addition, our proposed design takes up 0.84% to 3.28% (1732 LUTs to 6798 LUTs) and 5.04% to 10.08% (1916 (ALUT) to 3832 (ALUT)) when ported to Xilinx Virtex-5 and Altera Stratix-III FPGAs, respectively. Furthermore, our proposed design allows users to track remainders and to set customized thresholds of these remainders to be compatible with a specific application.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

Sign in / Sign up

Export Citation Format

Share Document