Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy

2014 ◽  
Author(s):  
Ralph Nathan ◽  
Bryan Anthonio ◽  
Shih-Lien Lu ◽  
Helia Naeimi ◽  
Daniel J. Sorin ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Floating Point ◽  
Architectural Support

ECIM: Exponent Computing in Memory for an Energy Efficient Heterogeneous Floating-Point DNN Training Processor

IEEE Micro ◽  
2021 ◽  
pp. 1-1
Author(s):  
Juhyoung Lee ◽  
Jihoon Kim ◽  
Wooyoung Jo ◽  
Sangyeob Kim ◽  
Sangjin Kim ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Floating Point

MULTIPROCESSOR RUNTIME SUPPORT FOR FINE-GRAINED, IRREGULAR DAGS

1995 ◽  
Vol 05 (04) ◽  
pp. 671-683 ◽  
Author(s):  
FREDERIC T. CHONG ◽  
SHAMIK D. SHARMA ◽  
ERIC A. BREWER ◽  
JOEL SALTZ
Keyword(s):  
Sparse Matrix ◽  
Directed Acyclic Graphs ◽  
Floating Point ◽  
Communication Overhead ◽  
Double Precision ◽  
Runtime Support ◽  
Architectural Support ◽  
Fine Grained ◽  
Banded Matrices ◽  
Acyclic Graphs

We examine multiprocessor runtime support for fine-grained, irregular directed acyclic graphs (DAGs) such as those that arise from sparse-matrix triangular solves. We conduct our experiments on the CM-5, whose lower latencies and active-message support allow us to achieve unprecedented speedups for a general multiprocessor. Where as previous implementations have maximum speedups of less than 4 on even simple banded matrices, we are able to obtain scalable performance on extremely small and irregular problems. On a matrix with only 5300 rows, we are able to achieve scalable performance with a speedup of 34 for 128 processors, resulting in an absolute performance of over 33 million double-precision floating point operations per second. We achieve these speedups with non-matrix-specific methods which are applicable to any DAG. We compare a range of run-time preprocessed and dynamic approaches on matrices from the Harwell-Boeing benchmark set. Although precomputed data distributions and execution schedules produce the best performance, we find that it is challenging to keep their cost low enough to make them worthwhile on small, fine-grained problems. Additionally, we find that a policy of frequent network polling can reduce communication overhead by a factor of three over the standard CM-5 policies. We present a detailed study of runtime overheads and demonstrate that send and receive processor overhead still dominate these applications on the CM-5. We conclude that these applications would highly benefit from architectural support for low-overhead communication.

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support

2007 ◽  
Vol 56 (5) ◽  
pp. 606-621 ◽  
Author(s):  
Francesco Poletti ◽  
Antonio Poggiali ◽  
Davide Bertozzi ◽  
Luca Benini ◽  
Pol Marchal ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Programming Models ◽  
Multiprocessor Systems ◽  
Embedded Computing ◽  
Architectural Support ◽  
Systems On Chip ◽  
On Chip
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