Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

ACM/IEEE SC 2002 Conference (SC'02) ◽

10.1109/sc.2002.10061 ◽

2002 ◽

Cited By ~ 11

Author(s):

T.L. Sterling ◽

H.P. Zima

Keyword(s):

Memory Architecture ◽

Multithreaded Processor ◽

Petaflops Computing

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Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules

Proceedings of the International Symposium on Memory Systems - MEMSYS '19 ◽

10.1145/3357526.3357541 ◽

2019 ◽

Cited By ~ 4

Author(s):

Onkar Patil ◽

Latchesar Ionkov ◽

Jason Lee ◽

Frank Mueller ◽

Michael Lang

Keyword(s):

Memory Architecture ◽

Performance Characterization ◽

Hybrid Memory ◽

Persistent Memory ◽

Memory Modules

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Technological Design of 3D NAND based Compute-in-Memory Architecture for GB-scale Deep Neural Network

IEEE Electron Device Letters ◽

10.1109/led.2020.3048101 ◽

2020 ◽

pp. 1-1

Author(s):

Wonbo Shim ◽

Shimeng Yu

Keyword(s):

Neural Network ◽

Deep Neural Network ◽

Memory Architecture ◽

Technological Design

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TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries

Proceedings of the 2020 on Great Lakes Symposium on VLSI ◽

10.1145/3386263.3406896 ◽

2020 ◽

Author(s):

Sheng Xu ◽

Xiaoming Chen ◽

Xuehai Qian ◽

Yinhe Han

Keyword(s):

Memory Architecture

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CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) ◽

10.1109/micro50266.2020.00038 ◽

2020 ◽

Author(s):

Dibei Chen ◽

Zhaoshi Li ◽

Tianzhu Xiong ◽

Zhiwei Liu ◽

Jun Yang ◽

...

Keyword(s):

Constant Time ◽

Memory Architecture

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Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics

2020 57th ACM/IEEE Design Automation Conference (DAC) ◽

10.1109/dac18072.2020.9218624 ◽

2020 ◽

Author(s):

Abraham Addisie ◽

Valeria Bertacco

Keyword(s):

Memory Architecture ◽

Graph Analytics

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MANNA: prototype of a distributed memory architecture with maximized sustained performance

Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing ◽

10.1109/empdp.1996.500600 ◽

2002 ◽

Cited By ~ 8

Author(s):

W.K. Giloi ◽

U. Bruening ◽

W. Schroeder-Preikschat

Keyword(s):

Distributed Memory ◽

Memory Architecture ◽

Sustained Performance ◽

Distributed Memory Architecture

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MASA: a multithreaded processor architecture for parallel symbolic computing

[1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings ◽

10.1109/isca.1988.5255 ◽

2003 ◽

Cited By ~ 46

Author(s):

R.H. Halstead ◽

T. Fujita

Keyword(s):

Processor Architecture ◽

Symbolic Computing ◽

Multithreaded Processor

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Parallelization Strategy for Elementary Morphological Operators on Graphs: Distance-Based Algorithms and Implementation on Multicore Shared-Memory Architecture

Journal of Mathematical Imaging and Vision ◽

10.1007/s10851-017-0737-1 ◽

2017 ◽

Vol 59 (1) ◽

pp. 136-160 ◽

Cited By ~ 2

Author(s):

Imane Youkana ◽

Jean Cousty ◽

Rachida Saouli ◽

Mohamed Akil

Keyword(s):

Shared Memory ◽

Memory Architecture ◽

Morphological Operators ◽

Parallelization Strategy

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On the Statistical Memory Architecture Exploration and Optimization

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0839 ◽

2015 ◽

Cited By ~ 1

Author(s):

Charalampos Antoniadis ◽

Georgios Karakonstantis ◽

Nestor Evmorfopoulos ◽

Andreas Burg ◽

George Stamoulis

Keyword(s):

Memory Architecture ◽

Architecture Exploration

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Parallel implementation for HSLO(3)-FDTD with message passing interface on Distributed Memory Architecture

2006 International Conference on Computing & Informatics ◽

10.1109/icoci.2006.5276531 ◽

2006 ◽

Author(s):

Mohammad Khatim Hasan ◽

Mohamed Othman ◽

Jalil Md Desa ◽

Zulkifly Abbas ◽

Jumat Sulaiman

Keyword(s):

Message Passing ◽

Message Passing Interface ◽

Distributed Memory ◽

Parallel Implementation ◽

Memory Architecture ◽

Distributed Memory Architecture

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