Power consumption in point-to-point interconnect architectures

2003 ◽  
Author(s):  
A.G. Ortiz ◽  
T. Murgan ◽  
L. Indrusiak ◽  
M. Glesner
Keyword(s):  
Power Consumption ◽  
Interconnect Architectures ◽  
Point To Point

scholarly journals High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures

2004 ◽  
Vol 1 (1) ◽  
pp. 23-31
Author(s):  
A. García-Ortiz ◽  
T. Murgan ◽  
L. Indrusiak ◽  
L. Kabulepa ◽  
M. Glesner
Keyword(s):  
Power Consumption ◽  
Real Data ◽  
Estimation Procedure ◽  
Levels Of Abstraction ◽  
Communication Architecture ◽  
Stochastic Data ◽  
High Level Estimation ◽  
Interconnect Architectures ◽  
Point To Point ◽  
High Level

As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point interconnect structures at high levels of abstraction. To model the effect of cross coupled capacitances, the spatial correlationbetween adjacent wire lines is considered together with the transition activity, and both are efficiently estimated using word-level statistics. Based on a set of increasing complexity stochastic data models, an analytical estimation procedure is proposed and validated with both synthetic and real data sets. Extensive bit level simulations have been carried out to show the accuracy of the proposed models.

scholarly journals Comparative Study of Hybrid Optimizations Technique for On-Chip Interconnect in Multimedia SoCs

2021 ◽  
Author(s):  
Jayshree ◽  
Gopalakrishnan Seetharaman ◽  
Debadatta Pati
Keyword(s):  
Power Consumption ◽  
Comparative Study ◽  
Optimization Technique ◽  
Schmitt Trigger ◽  
Deep Submicron ◽  
Multimedia Systems ◽  
Interconnect Architectures ◽  
On Chip ◽  
Point To Point ◽  
High Flexibility

This paper presents the design and analysis of on-chip interconnect architectures for real time Multimedia Systems-on-Chip (MSoC) targeting Internet of Things (IoT) applications. The interconnect architecture provides high flexibility in connection for hardware implementation of reconfigurable neural network. Due to technology’s miniaturization in ultra-deep submicron technology, the on-chip interconnect performance and power consumption become a bottle-neck. In this paper, the hybrid optimization technique is proposed to address these challenges using schmitt trigger as a repeater and tapering. Here, the proposed optimization technique is incorporated with a dedicated point to point based interconnection (PTP-BI) configuration. A comparative study with others without optimization technique (Model–I) shows the effectiveness of the proposed optimization technique (Model–II). The technology node scaling impacts are also analyzed for both techniques. Finally, the percentage reduction of latency and power consumption are evaluated in two different cases to observe the impacts of varying the interconnect length.

Design of an Intelligent Point-to-Point Swing Arm Controller

2013 ◽  
Vol 706-708 ◽  
pp. 712-715
Author(s):  
Wei Wei ◽  
Xiao Ying Zhao
Keyword(s):  
Power Consumption ◽  
Movement Time ◽  
Arm Movement ◽  
Solenoid Valve ◽  
Control Mode ◽  
Relay Control ◽  
Swing Arm ◽  
Valid Signal ◽  
Point To Point ◽  
The Moment

The point-to-point swing arm test is very important for large arms which have swing arm movement. Traditional point-to-point swing arm controller is relay control mode. The mode has many shortcomings, such as big volume, high power consumption, low stability, and so on. An intelligent point-to-point swing arm controller, using MCU as the control core, was designed for this reason. It was mainly composed of switch signal detecting module, solenoid valve drive module, USB storage interface module and MCU control module. According to the requirements of test, the controller was able to detect the valid signal of limit switch and control commutation operation of solenoid valve, meanwhile it could record the movement time between one point and another point, the time the arm swayed and the moment information, and these above information would be stored in USB memory. It has some advantages of small size, low power consumption, high stability and flexible functions.

scholarly journals Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

2019 ◽  
Vol 14 (2) ◽  
pp. 802
Author(s):  
Ng Yen Phing ◽  
M.N.Mohd Warip ◽  
Phaklen Ehkan ◽  
R Badlishah Ahmad ◽  
F.W. Zulkefli
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Cross Link ◽  
Ring Topology ◽  
Mesh Topology ◽  
Average Area ◽  
On Chip ◽  
Point To Point

<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

A Practical Approach to Provide Security in IEEE 802.15.4 Wireless Sensor Network

2014 ◽  
Vol 568-570 ◽  
pp. 503-507 ◽  
Author(s):  
Hui Lin
Keyword(s):  
Wireless Sensor Network ◽  
Power Consumption ◽  
Sensor Network ◽  
Ieee 802.15.4 ◽  
Sensor Nodes ◽  
Practical Approach ◽  
Wireless Sensor ◽  
Wireless Sensor Nodes ◽  
And Performance ◽  
Point To Point

During last years, IEEE 802.15.4 has been asserting itself as one of the most promising standards for Wireless Sensor Network. It includes a security sublayer, which provides a number of operations and procedures aimed at securing network communications. But providing security features and power consumption together face a trade-off. In spite of so many research works discussing IEEE 802.15.4 security service, so far not so many focus on their implementation and performance. This paper discusses some security aspects of IEEE 802.15.4, and presents a practical approach to secure point to point link between wireless sensor nodes in details, supporting all the security suites of the standard. The results demonstrated that our approach achieved significantly lower power consumption and higher performance in security.

Finding the Right Problems: Some HREM Applications to Interfaces

1984 ◽  
Vol 42 ◽  
pp. 376-379
Author(s):  
D. Cherns
Keyword(s):  
Grain Boundaries ◽  
High Resolution Electron Microscopy ◽  
Boundary Structure ◽  
Atomic Structures ◽  
Grain Boundary Structure ◽  
Resolution Electron ◽  
Point To Point ◽  
The Right ◽  
New Generation ◽  
Better Than

The use of high resolution electron microscopy (HREM) to determine the atomic structure of grain boundaries and interfaces is a topic of great current interest. Grain boundary structure has been considered for many years as central to an understanding of the mechanical and transport properties of materials. Some more recent attention has focussed on the atomic structures of metalsemiconductor interfaces which are believed to control electrical properties of contacts. The atomic structures of interfaces in semiconductor or metal multilayers is an area of growing interest for understanding the unusual electrical or mechanical properties which these new materials possess. However, although the point-to-point resolutions of currently available HREMs, ∼2-3Å, appear sufficient to solve many of these problems, few atomic models of grain boundaries and interfaces have been derived. Moreover, with a new generation of 300-400kV instruments promising resolutions in the 1.6-2.0 Å range, and resolutions better than 1.5Å expected from specialist instruments, it is an appropriate time to consider the usefulness of HREM for interface studies.

An x-ray microprobe based upon a close-coupled focal-spot / glass capillary arrangement

1992 ◽  
Vol 50 (2) ◽  
pp. 1758-1759
Author(s):  
D. A. Carpenter ◽  
M. A. Taylor
Keyword(s):  
Imaging Techniques ◽  
Fluorescence Analysis ◽  
High Sensitivity ◽  
Specimen Preparation ◽  
X Rays ◽  
Glass Capillary ◽  
Close Coupling ◽  
X Ray ◽  
Point To Point ◽  
Beam Damage

The development of intense sources of x rays has led to renewed interest in the use of microbeams of x rays in x-ray fluorescence analysis. Sparks pointed out that the use of x rays as a probe offered the advantages of high sensitivity, low detection limits, low beam damage, and large penetration depths with minimal specimen preparation or perturbation. In addition, the option of air operation provided special advantages for examination of hydrated systems or for nondestructive microanalysis of large specimens.The disadvantages of synchrotron sources prompted the development of laboratory-based instrumentation with various schemes to maximize the beam flux while maintaining small point-to-point resolution. Nichols and Ryon developed a microprobe using a rotating anode source and a modified microdiffractometer. Cross and Wherry showed that by close-coupling the x-ray source, specimen, and detector, good intensities could be obtained for beam sizes between 30 and 100μm. More importantly, both groups combined specimen scanning with modern imaging techniques for rapid element mapping.

Atomic structure imaging of the Si/SiO2 interface with high-resolution electron microscopy

1986 ◽  
Vol 44 ◽  
pp. 390-391
Author(s):  
J.L. Batstone ◽  
J.M. Gibson ◽  
Alice.E. White ◽  
K.T. Short
Keyword(s):  
Electron Microscopy ◽  
High Resolution ◽  
Atomic Structure ◽  
High Resolution Electron Microscopy ◽  
Medium Voltage ◽  
Voltage Electron ◽  
Resolution Electron ◽  
Structural Image ◽  
Electron Microscopes ◽  
Point To Point

High resolution electron microscopy (HREM) is a powerful tool for the determination of interface atomic structure. With the previous generation of HREM's of point-to-point resolution (rpp) >2.5Å, imaging of semiconductors in only <110> directions was possible. Useful imaging of other important zone axes became available with the advent of high voltage, high resolution microscopes with rpp <1.8Å, leading to a study of the NiSi2 interface. More recently, it was shown that images in <100>, <111> and <112> directions are easily obtainable from Si in the new medium voltage electron microscopes. We report here the examination of the important Si/Si02 interface with the use of a JEOL 4000EX HREM with rpp <1.8Å, in a <100> orientation. This represents a true structural image of this interface.

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