Non-serial Polyadic Dynamic Programming on a Data-Parallel Many-core Architecture

2011 ◽  
Author(s):  
Maryam Moazeni ◽  
Majid Sarrafzadeh ◽  
Alex A.T. Bui
Keyword(s):  
Dynamic Programming ◽  
Data Parallel ◽  
Many Core

scholarly journals Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs

2014 ◽  
Vol E97.D (11) ◽  
pp. 2827-2834 ◽  
Author(s):  
Ittetsu TANIGUCHI ◽  
Junya KAIDA ◽  
Takuji HIEDA ◽  
Yuko HARA-AZUMI ◽  
Hiroyuki TOMIYAMA
Keyword(s):  
Parallel Applications ◽  
Data Parallel ◽  
Dynamic Switching ◽  
Multiple Data ◽  
Many Core

scholarly journals Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs

2013 ◽  
Vol E96.D (10) ◽  
pp. 2268-2271
Author(s):  
Junya KAIDA ◽  
Yuko HARA-AZUMI ◽  
Takuji HIEDA ◽  
Ittetsu TANIGUCHI ◽  
Hiroyuki TOMIYAMA ◽  
...  
Keyword(s):  
Parallel Applications ◽  
Data Parallel ◽  
Multiple Data ◽  
Many Core

scholarly journals Exploring Many-Core Design Templates for FPGAs and ASICs

2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Ilia Lebedev ◽  
Christopher Fletcher ◽  
Shaoyi Cheng ◽  
James Martin ◽  
Austin Doupnik ◽  
...  
Keyword(s):  
Graphics Processing Unit ◽  
General Purpose ◽  
Coarse Grained ◽  
Processing Unit ◽  
Fine Grained ◽  
Data Parallel ◽  
Level Data ◽  
Graph Inference ◽  
High Level ◽  
Many Core

We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level programming language, (ii) supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii) reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

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