scholarly journals Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

2018 ◽  
Author(s):  
Ankit Agrawal ◽  
Renato Mancuso ◽  
Rodolfo Pellizzoni ◽  
Gerhard Fohler
Keyword(s):  
Real Time ◽  
Memory Bandwidth ◽  
Real Time Systems ◽  
Dynamic Memory ◽  
Time Systems

scholarly journals Hardware Dynamic Memory Manager for Hard Real-Time Systems

2019 ◽  
Vol 3 (4) ◽  
pp. 48-70
Author(s):  
Lukáš Kohútka ◽  
Lukáš Nagy ◽  
Viera Stopjaková
Keyword(s):  
Real Time ◽  
Systolic Array ◽  
Memory Allocation ◽  
Total Power ◽  
Real Time Systems ◽  
Clock Frequency ◽  
Dynamic Memory ◽  
Free Block ◽  
Hard Real Time ◽  
Time Systems

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems

2016 ◽  
Vol 65 (2) ◽  
pp. 601-614 ◽  
Author(s):  
Gang Yao ◽  
Heechul Yun ◽  
Zheng Pei Wu ◽  
Rodolfo Pellizzoni ◽  
Marco Caccamo ◽  
...  
Keyword(s):  
Real Time ◽  
Schedulability Analysis ◽  
Memory Bandwidth ◽  
Real Time Systems ◽  
Time Systems
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