scholarly journals An Upper Bound to the Lateness of Soft Real-Time Tasks Scheduled by EDF on Multiprocessors

Author(s):  
P. Valente ◽  
G. Lipari
Keyword(s):  
1993 ◽  
Vol 115 (1) ◽  
pp. 193-196
Author(s):  
S. S. Garimella ◽  
K. Srinivasan

Real-time state estimation of a linear dynamic system using an observer, in the presence of modeling errors in the system model used by the observer and uncertainty in the initial system states, is considered here. A guideline for designing observers for multioutput systems is established, based on an expression for an upper bound on the norm of the state estimation error derived in this paper. An example is presented to illustrate the usefulness of this guideline.


1996 ◽  
Vol 5 (4) ◽  
pp. 393-401 ◽  
Author(s):  
Deepak Tolani ◽  
Norman I. Badler

A simple inverse kinematics procedure is proposed for a seven degree of freedom model of the human arm. Two schemes are used to provide an additional constraint leading to closed-form analytical equations with an upper bound of two or four solutions, Multiple solutions can be evaluated on the basis of their proximity from the rest angles or the previous configuration of the arm. Empirical results demonstrate that the procedure is well suited for real-time applications.


2017 ◽  
Vol 6 (1) ◽  
pp. 29-38
Author(s):  
Sukemi Sukemi ◽  
Riyanto Riyanto

This research is purposed to increase computer function into a time driven to support real time system. This purposed would the processor can work according to determined time variable and can work optimally in a certained deadline. The first approachment to design some of processor that has a different bit space 64, 32, 16 and 8 bits. Each processor will be separated by selector/arbiter priority of a task. In addition, the design of the above processors are designed as a counter with varying levels of accuracy (variable precision computing). The selection is also done by using statistical control in the task are observed by the appearance of controller mounted on the front of the architecture bit space the second approach above. The last approach to ‘add’ certainty in the form of interval arithmetic precision cutting task that can be the upper bound and lower bound of the area (bounds). These four approachment can be structured orthogonally into a processor/several processors by introducing a new classifier that serves as a selector or a task arbiter. The results of the four approaches to prove that the processor is prepared by incorporating a variable bitspace adder selectors can provide optimality of 0.43%.


2016 ◽  
Vol 49 (3) ◽  
pp. 215-220 ◽  
Author(s):  
M. Samà ◽  
A. D’Ariano ◽  
D. Pacciarelli ◽  
F. Corman

2018 ◽  
Vol 11 (2) ◽  
pp. 152-160
Author(s):  
José Danilo Rairán Antolines

Given a sampled signal, in general, is not possible to compute its period, but just an approximation. We propose an algorithm to approximate the period, based on the Discrete Fourier Transform. If that transformation uses data length for multiples of the true period, some of its harmonics have null value. Thus, the best candidate to be a multiple of the period minimizes the value of those harmonics. The validation for noiseless data shows an upper bound in the error equal to a quarter of the time between two consecutive samples, whereas the result for noisy data demonstrates robustness. As application, the algorithm estimates the period of physiological signals, and tracks the frequency of the power grid in real time, which evidence its versatility


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